Datasheet
R01DS0216EJ0110
RX113 Group
Rev.1.10
Renesas MCUs
Mar 31, 2016
32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory,
USB 2.0 full-speed host/function/OTG, up to 12 comms channels, serial sound interface,
LCD controller/driver, capacitive touch sensing unit, 12-bit A/D, 12-bit D/A, RTC
Features
32-bit RX CPU core
32 MHz maximum operating frequency
Capable of 50 DMIPS when operating at 32 MHz
Accumulator handles 64-bit results (for a single instruction) from 32-
bit 32-bit operations
PLQP0100KB-A 14 14 mm, 0.5 mm pitch
Multiplication and division unit handles 32-bit 32-bit operations
PLQP0064KB-A 10 10 mm, 0.5 mm pitch
(multiplication instructions take one CPU clock cycle)
Fast interrupt
CISC Harvard architecture with five-stage pipeline
Variable-length instruction format, ultra-compact code
On-chip debugging circuit
Low power consumption functions PTLG0100JA-A 7 7 mm, 0.65 mm pitch
Operation from a single 1.8 to 3.6 V supply
Three low power consumption modes
Low power timer (LPT) that operates during the software standby
Up to 12 channels for communication
state
USB: USB 2.0 host/function/On-The-Go (OTG) (one channel), full-
Supply current
speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and
High-speed operating mode: 0.11 mA/MHz
BC (Battery Charger) supported
Software standby mode: 0.44 A
SCI: Asynchronous mode, clock synchronous mode, smart card
Recovery time from software standby mode: 4.8 s
interface (up to eight channels)
On-chip flash memory for code, no wait states
IrDA interface (one channel, in cooperation with SCI5)
2
Operation at 32 MHz, read cycle of 31.25 ns
I C bus interface: Transfer at up to 400 kbps, capable of SMBus
No wait states for reading at full CPU speed
operation (one channel)
128 to 512 Kbyte capacities
RSPI: Up to 16 Mbps (one channel)
Programmable at 1.8 V
Serial sound interface (SSI) (one channel)
For instructions and operands
Up to 14 extended-function timers
On-chip data flash memory
16-bit MTU: Input capture/output compare, complementary PWM
8 Kbytes
output, phase counting mode
1,000,000 Erase/Write cycles (typ.)
(six channels)
BGO (Background Operation)
8-bit TMR (four channels)
16-bit CMT (four channels)
On-chip SRAM, no wait states
32 and 64 Kbyte capacities LCD controller/driver
Segment signal output common signal output:
Data transfer controller (DTC)
40 4, 36 8
Four transfer modes
On-chip voltage boost circuit, contrast adjustment, and 5-V panel
Transfer can be set for each interrupt source.
supported
Event link controller (ELC)
Blinking function
Module operation can be initiated by event signals without going
12-bit A/D converter
through interrupts.
Up to 17 channels
Link operation between modules is possible while the CPU is
1.0 s minimum conversion speed
sleeping.
Double trigger (data duplication) function for motor control
Reset and power supply voltage management
12-bit D/A converter
Six types including Power-On Reset (POR)
Two channels
Low voltage detection (LVD) with voltage settings
Comparator B
Clock functions
Two channels
External clock input frequency: Up to 20 MHz
Main clock oscillator frequency: 1 to 20 MHz Capacitive touch sensing unit (CTSU)
Sub-clock oscillator frequency: 32.768 kHz
Detection pins: 12 channels (for 100 pins only)
PLL circuit input: 4 to 8 MHz
High-sensitive electrostatic capacitance detection using
Low-speed on-chip oscillator: 4 MHz
self-capacitance and mutual capacitance methods
High-speed on-chip oscillator: 32 MHz 1% ( 20 to 85C)
On-chip noise canceller that enables high tolerance to disturbance
USB-dedicated PLL circuit: 6 and 8 MHz
noise
IWDT-dedicated on-chip oscillator: 15 kHz
Also supports a mutual capacitance method that allows touch
Generate a dedicated 32.768-kHz clock for the RTC
channels to be increased with low pin counts
On-chip clock frequency accuracy measurement circuit (CAC)
Temperature sensor
Realtime clock (RTC)
General I/O ports
30-second, leap year, and error adjustment functions
5-V tolerant, open drain, input pull-up
Calendar count mode or binary count mode selectable
Multi-function pin controller (MPC)
Capable of initiating exit from software standby mode
Multiple I/O pins can be selected for peripheral functions.
Independent watchdog timer (IWDT)
Unique ID
15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
32-byte ID code for the MCU
On-chip functions for IEC 60730 compliance
Operating temperature range
Clock frequency accuracy measurement circuit, IWDT, functions to
40 to 85 C
assist in RAM testing, etc.
40 to 105C
R01DS0216EJ0110 Rev.1.10 Page 1 of 131
Mar 31, 2016RX113 Group 1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1 Outline of Specifications (1/3)
Classification Module/Function Description
CPU CPU Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit 32-bit 64-bit
On-chip divider: 32-bit 32-bit 32 bits
Barrel shifter: 32 bits
Memory ROM Capacity: 128 K /256 K /384 K /512 Kbytes
32 MHz, no-wait memory access
Programming/erasing method:
Serial programming (asynchronous serial communication/USB communication), self-programming
RAM Capacity: 32 K /64 Kbytes
32 MHz, no-wait memory access
E2 DataFlash Capacity: 8 Kbytes
Number of erase/write cycles: 1,000,000 (typ)
MCU operating mode Single-chip mode
Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, USB-dedicated PLL frequency synthesizer, and IWDT-dedicated on-chip
oscillator
Oscillation stop detection: Available
Clock frequency accuracy measurement circuit (CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,
64).
Resets RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
Voltage detection Voltage detection circuit When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
(LVDAa) is generated.
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Low power Low power consumption Module stop function
consumption functions Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Function for lower operating Operating power control modes
power consumption High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt Interrupt controller (ICUb) Interrupt vectors: 120
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt,
and IWDT interrupt)
16 levels specifiable for the order of priority
R01DS0216EJ0110 Rev.1.10 Page 2 of 131
Mar 31, 2016