Datasheet RX220 Group R01DS0130EJ0110 Renesas MCUs Rev.1.10 Dec 20, 2013 32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory, 12-bit A/D, ELC, MPC, IrDA, RTC, up to 7 comms channels incorporating functions for IEC60730 compliance Features 32-bit RX CPU core Max. operating frequency: 32 MHz Capable of 49 DMIPS in operation at 32 MHz PLQP0100KB-A 14 14 mm, 0.5-mm pitch PLQP0064KB-A 10 10 mm, 0.5-mm pitch Accumulator handles 64-bit results (for a single PLQP0048KB-A 7 7 mm, 0.5-mm pitch instruction) from 32- 32-bit operations PLQP0064GA-A 14 14 mm, 0.8-mm pitch Multiplication and division unit handles 32- 32-bit operations (multiplication instructions take one CPU Independent watchdog timer clock cycle) 125-kHz on-chip oscillator produces a dedicated clock Fast interrupt signal to drive IWDT operation. CISC Harvard architecture with 5-stage pipeline Variable-length instructions, ultra-compact code Useful functions for IEC60730 compliance On-chip debugging circuit Self-diagnostic and disconnection-detection assistance functions for the A/D converter, clock-frequency Low-power design and architecture accuracy-measurement circuit, independent watchdog Operation from a single 1.62-V to 5.5-V supply timer, functions to assist in RAM testing, etc. 1.62-V operation available (at up to 8 MHz) Three low-power modes Up to seven communications channels SCI with many useful functions (up to five channels) On-chip flash memory for code, no wait states Asynchronous mode, clock synchronous mode, smart 32-MHz operation, 31.25-ns read cycle card interface mode No wait states for reading at full CPU speed IrDA Interface (one channel, in cooperation with the Up to 256-Kbyte capacity SCI5) User code programmable via the SCI 2 I C bus interface: Transfer at up to 400 kbps, capable of Programmable at 1.62 V SMBus operation (one channel) For instructions and operands RSPI (one channel) On-chip data flash memory Up to 14 extended-function timers 8 Kbytes (Number of times of reprogramming: 100,000) 16-bit MTU: input capture, output capture, Erasing and programming impose no load on the CPU. complementary PWM output, phase counting mode On-chip SRAM, no wait states (six channels) Up to 16-Kbyte size capacity 8-bit TMR (four channels) DMA 16-bit compare-match timers (four channels) DMAC: Incorporates four channels 12-bit A/D converter DTC: Four transfer modes Capable of conversion within 1.56 s ELC Self-diagnostic function and analog input disconnection Module operation can be initiated by event signals detection assistance function without going through interrupts. Analog comparator Modules can operate while the CPU is sleeping. General I/O ports Reset and supply management 5-V tolerant, open drain, input pull-up, switching of Seven types of reset, including the power-on reset (POR) driving ability Low voltage detection (LVD) with voltage settings MPC Clock functions Multiple locations are selectable for I/O pins of Frequency of external clock: Up to 20 MHz peripheral functions Frequency of the oscillator for sub-clock generation: 32.768 kHz Operating temp. range 40 C to +85C On-chip low- and high-speed oscillators, dedicated on- 40 C to +105C chip low-speed oscillator for the IWDT Generation of a dedicated 32.768-kHz clock for the RTC Clock frequency accuracy measurement circuit (CAC) Real-time clock Adjustment functions (30 seconds, leap year, and error) Year and month display or 32-bit second display (binary counter) is selectable R01DS0130EJ0110 Rev.1.10 Page 1 of 105 Dec 20, 2013RX220 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1 / 3) Classification Module/Function Description CPU CPU Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits Memory ROM Capacity: 32 K/64 K/128 K/256 Kbytes 32 MHz, no-wait memory access On-board programming: 3 types RAM Capacity: 4 K/8 K/16 Kbytes 32 MHz, no-wait memory access E2 DataFlash E2 DataFlash capacity: 8 Kbytes MCU operating mode Single-chip mode Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator, and IWDT-dedicated on-chip oscillator Oscillation stop detection Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC) Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and flashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 32 MHz (at max.) Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at max.) The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 32 MHz (at max.) Reset RES pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset Voltage detection Voltage detection circuit When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt (LVDAa) is generated. Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels Low power Low power consumption Module stop function consumption facilities Three low power consumption modes Sleep mode, all-module clock stop mode, and software standby mode Function for lower Four operating power control modes operating power Middle-speed operating mode 1A, middle-speed operating mode 1B, low-speed operating mode 1, consumption low-speed operating mode 2 Interrupt Interrupt controller (ICUb) Interrupt vectors: 106 External interrupts: 9 (NMI, IRQ0 to IRQ7 pins) Non-maskable interrupts: 5 (the NMI pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and IWDT interrupt) 16 levels specifiable for the order of priority R01DS0130EJ0110 Rev.1.10 Page 2 of 105 Dec 20, 2013