DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST SSTE32882HLB AND QUAD CHIP SELECT has occurred on the open-drain ERROUT pin (active low). The Description convention is even parity i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock combined with the parity input bit. To calculate parity, all driver with parity is designed for 1.35V and 1.5V VDD operation. DIMM-independent D-inputs must be tied to a known logic state. All inputs are 1.35V and 1.5V CMOS compatible, except the The DIMM-dependent signals (DCKEn, DODTn, and DCSn) are reset (RESET) and MIRROR inputs which are LVCMOS. All not included in the parity check computation. outputs are 1.35V and 1.5V CMOS edge-controlled drivers optimized to drive single terminated 25 to 50 traces in DDR3 To ensure defined outputs from the register before a stable clock RDIMM applications, except the open-drain error (ERROUT) has been supplied, RESET must be held in the low state during output. The clock outputs (Yn and Yn) and control net outputs power-up. QnCKEn, QnCSn and QnODTn are designed with a different The SSTE32882HLB is available in a 176-ball BGA with strength and skew to compensate for different loading and 0.65mm ball pitch in a 11 x 20 grid. It is also available in a equalize signal travel speed. 176-ball Thin-Profile Fine-Pitch BGA with 0.65mm ball pitch in The SSTE32882HLB has two basic modes of operation an 8x22 grid. The device pinout supports outputs on the outer two associated with the Quad Chip Select Enable (QCSEN) input. left and right columns to support easy DIMM signal routing. When the QCSEN input pin is open (or pulled high), the Corresponding inputs are placed in a-way that two devices can be component has two chip select inputs, DCS0 and DCS1, and two placed back-to-back for four Rank modules while the data inputs copies of each chip select output, QACS0, QACS1, QBCS0 and share the same vias. Each input and output is located close to an QBCS1. This is theQuadCS disable mode. When the associated no ball position or on the outer two rows to allow low QCSEN input pin is pulled low, the component has four chip cost via technology combined with the small 0.65mm ball pitch. select inputs DCS 3:0 , and four chip select outputs, QCS 3:0 . This is theQuadCS enable mode. Through the remainder of this specification, DCS n:0 will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS n:0 will indicate all of the chip select outputs. The SSTE32882HLB includes a high-performance, low-jitter, low-skew buffer that distributes a differential clock input (CK and CK) to four differential pairs of clock outputs (Yn and Yn), and to one differential pair of feedback clock outputs (FBOUT and FBOUT). The clock outputs are controlled by the input clocks (CK and CK), the feedback clocks (FBIN and FBIN), and the analog power inputs (AVDD and AVSS). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The SSTE32882HLB operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low. The data is either driven to the corresponding device outputs if exactly one of the DCS n:0 input signals is driven low. Based on the control register settings, the device can change its output characterisitics to match different DIMM net topologies. The timing can be changed to compensate for different flight time of signals within the target application. By disabling unused outputs the power consumption is reduced. The SSTE32882HLB accepts a parity bit from the memory controller on the parity (PAR IN) input, compares it with the data received on the DIMM-independent data inputs (DAn, DBAn, DRAS, DCAS, and DWE), and indicates whether a parity error 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 1 SSTE32882HLB 7201/14SSTE32882HLB 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE Features Pinout optimizes DDR3 RDIMM PCB layout 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs Supports LVCMOS switching levels on the RESET and MIRROR inputs Checks priority on DIMM-independent data inputs Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations and MRS command pass-through Supports CKE Power Down operation modes Supports Quad Chip Select operation features RESET input disables differential input recievers, resets all registers, and disables all output drivers except ERROUT and QnCKEn Provides access to internal control words for configuring the device features and adapting in different RDIMM and system applications Latch-up performance exceeds 100mA ESD > 2000V per MIL-STD883, Method 3015 ESD > 200V using machine model (c = 200pF, R = 0) Available in 176 Ball Grid Array package 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 2 SSTE32882HLB 7201/14