DATASHEET X5083 FN8127 Rev 4.00 CPU Supervisor with 8Kbit SPI EEPROM November 12, 2015 This device combines four popular functions, Power-on Reset Features Control, Watchdog Timer, Supply Voltage Supervision, and Low V detection and reset assertion CC Block Lock Serial EEPROM Memory in one package. This - Four standard reset threshold voltages combination lowers system cost, reduces board space 4.63V, 4.38V, 2.93V, 2.63V requirements, and increases reliability. - Re-program low V reset threshold voltage using CC Applying power to the device activates the power-on reset special programming sequence circuit which holds RESET active for a period of time. This - Reset signal valid to V = 1V CC allows the power supply and oscillator to stabilize before the Selectable time out watchdog timer processor can execute code. Long battery life with low power consumption The Watchdog Timer provides an independent protection - <50A max standby current, watchdog on mechanism for microcontrollers. When the microcontroller fails to - <1A max standby current, watchdog off restart a timer within a selectable time out interval, the device - <400A max active current during read activates the RESET signal. The user selects the interval from three preset values. Once selected, the interval does 8Kbits of EEPROM not change, even after cycling the power. Save critical data with Block Lock memory The devices low V detection circuitry protects the users CC - Block lock first or last page, any 1/4 or lower 1/2 of system from low voltage conditions, resetting the system EEPROM array when V falls below the minimum V trip point. RESET is CC CC Built-in inadvertent write protection asserted until V returns to the proper operating level and CC - Write enable latch stabilizes. Five industry standard V thresholds are TRIP - Write protect pin available, however, Intersils unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine- SPI Interface - 3.3MHz clock rate tune the threshold for applications requiring higher precision. Minimize programming time - 16 byte page write mode Pinouts - 5ms write cycle time (typical) 8 LD TSSOP SPI modes (0,0 & 1,1) RESET SCK 1 8 Available packages V SI 2 7 CC X5083 - 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP CS/WDI V 3 6 SS WP SO 4 5 Pb-free plus anneal available (RoHS compliant) Applications Communications Equipment 8 LD SOIC, 8 LD PDIP - Routers, Hubs, Switches - Set Top Boxes 1 8 V CS/WDI CC SO 2 7 RESET Industrial Systems X5083 WP 3 6 SCK - Process Control V SI SS 4 5 - Intelligent Instrumentation Computer Systems - Desktop Computers - Network Servers Battery Powered Equipment FN8127 Rev 4.00 Page 1 of 21 November 12, 2015 NO LONGER AVAILABLE OR SUPPORTEDX5083 Typical Application 2.7-5.0V VCC uC VCC 10K X5083 RESET RESET CS SCK SPI SI SO WP VSS VSS Block Diagram POR AND LOW V + VOLTAGE RESET CC RESET (X5083) GENERATION - V TRIP RESET & WATCHDOG TIMEBASE X5083 WATCHDOG WATCHDOG STANDARD V LEVEL SUFFIX TRIP TIMER TRANSITION DETECTOR RESET 4.63V (+/-2.5%) -4.5A 4.38V (+/-2.5%) -4.5 CS/WDI STATUS COMMAND 2.93V (+/-2.5%) -2.7A REGISTER SI DECODE & 2.63V (+/-2.5%) -2.7 SO CONTROL EEPROM LOGIC ARRAY See Ordering Information on page 3 for SCK 8KBITS more details PROTECT LOGIC WP For Custom Settings, call Intersil. FN8127 Rev 4.00 Page 2 of 21 November 12, 2015