DATASHEET X9252 FN8167 Rev 3.00 Low Power + Quad 256-tap + 2-Wire Bus + Up/Down Interface Quad July 24, 2014 Digitally-Controlled (XDCP) Potentiometer The X9252 integrates 4 digitally controlled potentiometers Features (XDCP) on a monolithic CMOS integrated circuit. Quad Solid State Potentiometer The digitally controlled potentiometers are implemented 256 Wiper Tap Points-0.4% Resolution using 255 resistive elements in a series array. Between each pair of elements are tap points connected to wiper terminals 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer through switches. The position of each wiper on the array is controlled by the user through the Up/Down (U/D) or 2-wire Up/Down Interface for Individual Potentiometers bus interface. The wiper of each potentiometer has an Wiper Resistance: 40 Typical associated volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers (DRs) that can be directly written NonVolatile Storage of Wiper Positions to and read by the user. The contents of the WCR controls Power On Recall. Loads Saved Wiper Position on the position of the wiper on the resistor array through the Power-Up. switches. At power-up, the device recalls the contents of the Standby Current < 100A Max default data registers DR00, DR10, DR20, DR30, to the corresponding WCR. Maximum Wiper Current: 3mA Each DCP can be used as a three-terminal potentiometer or V : 2.7V to 5.5V Operation CC as a two terminal variable resistor in a wide variety of 2.8k and 10k Version of Total Pot Resistance applications including the programming of bias voltages, the implementation of ladder networks, and three resistor Endurance: 100,000 Data Changes per Bit per Register programmable networks. 100 yr. Data Retention 24 Ld TSSOP Pb-Free (RoHS Compliant) Pinout X9252 (24 LD TSSOP) TOP VIEW 24 DS1 DS0 1 23 SCL A0 2 22 R R 3 L2 W3 21 R R H2 H3 4 20 R R 5 W2 L3 CS U/D 19 6 V V 18 CC 7 SS 8 R R W1 L0 17 9 R R 16 H1 H0 10 R R L1 W0 15 A1 11 A2 14 13 SDA 12 WP FN8167 Rev 3.00 Page 1 of 19 July 24, 2014X9252 Ordering Information PART NUMBER PART R TEMP RANGE PACKAGE PKG. TOTAL (Notes 1, 2) MARKING (k ) (C) (Pb-free) DWG. X9252YV24IZ-2.7 X9252YV ZG 2.8 -40 to +85 24 Ld TSSOP (4.4mm) M24.173 X9252WV24IZ-2.7 X9252WV ZG 10 -40 to +85 24 Ld TSSOP (4.4mm) M24.173 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for X9252. For more information on MSL please see tech brief TB363 Functional Diagram R R R V R H0 H1 H2 H3 CC A2 2-Wire A1 Interface DCP0 DCP1 DCP2 DCP3 WCR0 WCR1 WCR2 WCR3 A0 DR10 DR20 DR30 DR00 DR11 DR31 DR01 DR21 POWER-UP, SDA DR02 DR12 DR22 DR32 INTERFACE DR13 DR23 DR33 DR03 CONTROL SCL AND STATUS Up-Down Interface DS0 DS1 CS U/D V SS R R R R R R R WP R L1 L3 W0 L0 W1 W2 L2 W3 Pin Descriptions PIN SYMBOL DESCRIPTION 1, 24 DS0, DS1 DCP select for Up/Down interface. 2, 14, 11 A0, A1, A2 Device address for 2-wire bus. 3R Wiper terminal of DCP3. W3 4R High terminal of DCP3. H3 5R Low terminal of DCP3. L3 6U/D Increment/decrement for up/down interface. 7V System supply voltage CC 8R Low terminal of DCP0. L0 9R High terminal of DCP0. H0 10 R Wiper terminal of DCP0. W0 12 WP Hardware write protect 13 SDA Serial data input/output for 2-wire bus. 15 R Low terminal of DCP1. L1 16 R High terminal of DCP1. H1 17 R Wiper terminal DCP1. W1 18 V System ground SS FN8167 Rev 3.00 Page 2 of 19 July 24, 2014