X9448 Mixed Signal with 2-Wire Interface Data Sheet April 18, 2005 FN8201.0 DESCRIPTION Dual Digitally Controlled Potentiometer (XDCP) & Voltage Comparator The X9448 integrates two nonvolatile digitally con- trolled potentiometers (XDCP) and two voltage com- FEATURES parators on a CMOS monolithic microcircuit. Two digitally controlled potentiometers and two The X9448 contains two resistor arrays, each com- voltage comparators in one package posed of 63 resistive elements. Between each ele- 2-wire serial interface ment and at either end are tap points accessible to the Register oriented format wiper elements. The position of the wiper element on Direct read/write wiper position the array is controlled by the user through the two wire Store as many as four positions per pot serial bus interface. Fast response comparator Enable, latch, or shutdown comparator outputs Each potentiometer has an associated voltage com- through ACR parator. The comparator compares the external input Auto-recall of WCR and ACR data from R0 voltage V with the wiper voltage V and sets the out- NI W Hardware write protection, WP put voltage level to a logic high or low. Separate analog and digital/system supplies Each resistor array and comparator has associated Direct write cell with it a wiper counter register (WCR), analog control Endurance100,000 data changes per bit per register (ACR), and eight 6-bit data registers that can register be directly written and read by the user. The contents Register data retention100 years of the wiper counter register controls the position of 16-bytes of EEPROM memory the wiper on the resistor array. The contents of the Power saving feature and low noise analog control register controls the comparator and its Two 10k or two 2.5k potentiometers output. The potentiometer is programmed with a Resolution: 64 taps each pot 2-wire serial interface. 24-lead TSSOP and 24-lead SOIC packages BLOCK DIAGRAM V H (0,1) (R -R ) WCR 0 3 0,1 0,1 WP V L (0,1) V SCL W (0,1) SDA Interface and A0 V Control NI (0,1) A1 Circuitry A2 A3 + (R -R ) V ACR 0 3 0,1 OUT (0,1) 0,1 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-352-6832 Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT X9418X9448 PIN DESCRIPTIONS Hardware Write Protect Input WP The WP pin when low prevents nonvolatile writes to Host Interface Pins the wiper counter and analog control registers. Serial Clock (SCL) Analog Supplies V+, V- The SCL input is used to clock data into and out of the The analog supplies V+, V- are the supply voltages for X9448. the XDCP analog section and the voltage comparators. Serial Data (SDA) System Supply V and Ground V CC SS SDA is a bidirectional pin used to transfer data into The system supply V and its reference V is used CC SS and out of the device. It is an open drain output and to bias the interface and control circuits. may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires PIN CONFIGURATION the use of a pull-up resistor. For selecting typical val- ues, refer to the guidelines for calculating typical val- SOIC ues on the bus pull-up resistors graph. V 1 V+ CC 24 Device Address (A - A ) V 0 3 2 V L0 23 OUT0 V The address inputs are used to set the least significant 3 V H0 22 NI0 4 bits of the 8-bit slave address. A match in the slave V 4 NC W0 21 address serial data stream must be made with the A 5 20 A0 2 address input in order to initiate communication with WP 6 NC 19 the X9448. A maximum of 16 devices may share the X9448 SDA 7 18 A 3 same 2-wire serial bus. A1 8 SCL 17 V 9 16 NC Potentiometer Pins L1 10 V 15 V H1 NI1 V (V - V ), V (V - V ) V 11 H H0 H1 L L0 L1 W1 14 V OUT1 The V and V inputs are equivalent to the terminal con- V 13 H L SS 12 V- nections on either end of a mechanical potentiometer. V (V - V ) TSSOP W W0 W1 The wiper output is equivalent to the wiper output of a SDA WP 1 24 mechanical potentiometer and is connected to the A 1 A 2 2 23 inverting input of the voltage comparator. V L1 V 3 W0 22 V H1 V 4 H0 Comparator and Device Pins 21 V W1 V 5 L0 20 V V Voltage Input V , V SS 6 CC NI0 NI1 19 X9448 NC NC 7 V and V are the input voltages to the plus (non- 18 NI0 NI1 V- inverting) inputs of the two comparators. 8 V+ 17 V OUT1 9 V 16 OUT0 Buffered Voltage Outputs V , V V OUT0 OUT1 NI1 10 V NI0 15 The V , and V are the buffered voltage OUT0 OUT1 SCL 11 A 0 14 comparator outputs enabled by respective bits in the A 13 NC 3 12 volatile analog control register. FN8201.0 2 April 18, 2005