X9455 Data Sheet July 28, 2006 FN8202.1 Dual Two-wiper Digitally-Controlled Features (XDCP) Potentiometer Dual two-wiper solid state potentiometer The X9455 integrates 2 digitally controlled potentiometers 256 resistor tap points-0.4% resolution (XDCP), each one with dual wipers, on a monolithic CMOS 2-wire serial interface for write, read, and transfer integrated circuit. operations of the potentiometer The digitally controlled potentiometer is implemented using Up/Down interface for individual potentiometer wipers 255 resistive elements in a series array. Between each element are tap points connected to wiper terminals through Wiper resistance, 40 typical switches. The position of each wiper on the array is Non-volatile storage of wiper positions controlled by the user through the U/D or 2-wire bus interface. Each potentiometer wiper has associated with it Power on recall loads saved wiper position on power-up. two volatile Wiper Counter Register (WCR) and each WCR Standby current < 20A Max has associated with it four non-volatile Data Registers that Maximum wiper current: 3mA can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor V : 2.7V to 5.5V operation CC array though the switches. The contents of the default data 2.8k ,10k , 50k , 100k version of total pot resistance registers (DR0A0, DR0B0, DR1A0, DR1B0) are loaded into the WCR on power up. Endurance: 100,000 data changes per bit per register The DCP can be used as a four-terminal potentiometer in a 100 yr. data retention wide variety of applications including the programming of 24 Ld TSSOP bias voltages, window comparators, and three resistor Pb-free plus anneal available (RoHS compliant) programmable networks. Pinout X9455 (24 LD TSSOP) TOP VIEW 24 DS1 1 DS0 23 SCL 2 A0 22 RL1 RW0B 3 NC 21 RH1 4 20 RW1A 5 NC 19 CS 6 U/D X9455 18 Vss 7 Vcc RW1B 8 RL0 17 NC 9 RH0 16 10 NC RW0A 15 A1 11 14 A2 12 13 SDA WP CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT c t u T ch ic l Support Center at ontac o r e n a 8 IL or www intersil.com/tsc 1- 88-INTERS .X9455 Ordering Information PART V LIMITS CC PART NUMBER MARKING (V) R (k) TEMP RANGE (C) PACKAGE PKG. DWG. TOTAL X9455TV24I-2.7 X9455TV G 2.7 to 5.5 100 -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9455TV24IZ-2.7 (Note) X9455TV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9455UV24I-2.7 X9455UV G 50 -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9455UV24IZ-2.7 (Note) X9455UV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9455WV24I-2.7 X9455WV G 10 -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9455WV24IZ-2.7 (Note) X9455WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9455YV24I-2.7 X9455YV G 2.8 -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9455YV24IZ-2.7 (Note) X9455YV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Functional Diagram R R H0 H1 V CC A2 2-wire A1 Interface A0 DCP0 DCP1 WCR0A WCR0B WCR1A WCR1B SDA DR0A0 DR0B0 DR1A0 DR1B0 DR0A1 DR0B1 DR1A1 DR1B1 POWERUP, SCL DR0A2 DR0B2 DR1A2 DR1B2 INTERFACE CONTROL AND DR0A3 DR0B3 DR1A3 DR1B3 Up/Down STATUS Interface DS0 DS1 CS U/D V SS WP R R R R R R W0B L0 L1 W0A W1A W1B FN8202.1 2 July 28, 2006