35
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Platform Flash In-System Programmable
Configuration PROMs
DS123 (v2.19) June 6, 2016 Product Specification
Features
In-System Programmable PROMs for Configuration of XCF01S/XCF02S/XCF04S
Xilinx FPGAs
3.3V Supply Voltage
Low-Power Advanced CMOS NOR Flash Process
Serial FPGA Configuration Interface
Endurance of 20,000 Program/Erase Cycles
Available in Small-Footprint VO20 and VOG20
Operation over Full Industrial Temperature Range Packages
(40C to +85C)
XCF08P/XCF16P/XCF32P
IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
1.8V Supply Voltage
Support for Programming, Prototyping, and Testing
Serial or Parallel FPGA Configuration Interface
JTAG Command Initiation of Standard FPGA
Available in Small-Footprint VOG48, FS48, and
Configuration
FSG48 Packages
Cascadable for Storing Longer or Multiple Bitstreams
Design Revision Technology Enables Storing and
Dedicated Boundary-Scan (JTAG) I/O Power Supply (V )
CCJ
Accessing Multiple Design Revisions for
I/O Pins Compatible with Voltage Levels Ranging From Configuration
1.8V to 3.3V
Built-In Data Decompressor Compatible with Xilinx
Design Support Using the Xilinx ISE Alliance and Advanced Compression Technology
Foundation Software Packages
Description
Xilinx introduces the Platform Flash series of in-system 8 Mb PROMs that support Master Serial, Slave Serial,
programmable configuration PROMs. Available in Master SelectMAP, and Slave SelectMAP FPGA
1 to 32 Mb densities, these PROMs provide an easy-to-use, configuration modes (Figure 2, page 2).
cost-effective, and reprogrammable method for storing large
When driven from a stable, external clock, the PROMs can
Xilinx FPGA configuration bitstreams. The Platform Flash
output data at rates up to 33 MHz. Refer toAC Electrical
PROM series includes both the 3.3V XCFxxS PROM and
Characteristics page 16 for timing considerations.
the 1.8V XCFxxP PROM. The XCFxxS version includes
4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial A summary of the Platform Flash PROM family members
and Slave Serial FPGA configuration modes (Figure 1, and supported features is shown in Table 1.
page 2). The XCFxxP version includes 32 Mb, 16 Mb, and
Table 1: Platform Flash PROM Features
Density V V Range V Range Program In-system Serial Parallel Design
CCINT CCO CCJ
Device Packages Compression
via JTAG
(Mb) (V) (V) (V) Config. Config. Revisioning
XCF01S 1 3.3 1.8 3.3 2.5 3.3 VO20/VOG20
XCF02S 2 3.3 1.8 3.3 2.5 3.3 VO20/VOG20
XCF04S 4 3.3 1.8 3.3 2.5 3.3 VO20/VOG20
VO48/VOG48
(1)
XCF08P 8 1.8 1.8 3.3 2.5 3.3
FS48/FSG48
VO48/VOG48
XCF16P 16 1.8 1.8 3.3 2.5 3.3
FS48/FSG48
VO48/VOG48
XCF32P 32 1.8 1.8 3.3 2.5 3.3
FS48/FSG48
Notes:
1. XCF08P supports storage of a design revision only when cascaded with another XCFxxP PROM. SeeDesign Revisioning page 8 for details.
Copyright 20032016 Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. All other trademarks are the property of their respective owners.
DS123 (v2.19) June 6, 2016 www.xilinx.com
Product Specification 1R
Platform Flash In-System Programmable Configuration PROMs
X-Ref Target - Figure 1
CLK CE OE/RESET
TCK
Data
Control
CEO
Serial
TMS
and Memory
Interface
Data
JTAG
TDI DATA (D0)
Address
Interface Serial Mode
TDO
CF
ds123_01_30603
Figure 1: XCFxxS Platform Flash PROM Block Diagram
X-Ref Target - Figure 2FI
CLK CE EN_EXT_SEL OE/RESET BUSY
OSC
CLKOUT
Decompressor
Control Serial
TCK
CEO
Data
TMS and or
Memory
TDI
DATA (D0)
JTAG Parallel
Address
TDO (Serial/Parallel Mode)
Interface Interface
Data
D[1:7]
(Parallel Mode)
DS123_19_031908
CF REV_SEL [1:0]
Figure 2: XCFxxP Platform Flash PROM Block Diagram
When the FPGA is in Master Serial mode, it generates a short access time after each rising clock edge. The data is
configuration clock that drives the PROM. With CF High, a clocked into the FPGA on the following rising edge of the
short access time after CE and OE are enabled, data is CCLK. A free-running oscillator can be used in the Slave
available on the PROM DATA (D0) pin that is connected to Parallel/Slave SelectMAP mode.
the FPGA DIN pin. New data is available a short access
The XCFxxP version of the Platform Flash PROM provides
time after each rising clock edge. The FPGA generates the
additional advanced features. A built-in data decompressor
appropriate number of clock pulses to complete the
supports utilizing compressed PROM files, and design
configuration.
revisioning allows multiple design revisions to be stored on
When the FPGA is in Slave Serial mode, the PROM and the a single PROM or stored across several PROMs. For design
FPGA are both clocked by an external clock source, or revisioning, external pins or internal control bits are used to
optionally, for the XCFxxP PROM only, the PROM can be select the active design revision.
used to drive the FPGAs configuration clock.
Multiple Platform Flash PROM devices can be cascaded to
The XCFxxP version of the Platform Flash PROM also support the larger configuration files required when
supports Master SelectMAP and Slave SelectMAP (or targeting larger FPGA devices or targeting multiple FPGAs
Slave Parallel) FPGA configuration modes. When the FPGA daisy chained together. When utilizing the advanced
is in Master SelectMAP mode, the FPGA generates a features for the XCFxxP Platform Flash PROM, such as
configuration clock that drives the PROM. When the FPGA design revisioning, programming files which span cascaded
is in Slave SelectMAP Mode, either an external oscillator PROM devices can only be created for cascaded chains
generates the configuration clock that drives the PROM and containing only XCFxxP PROMs. If the advanced XCFxxP
the FPGA, or optionally, the XCFxxP PROM can be used to features are not enabled, then the cascaded chain can
drive the FPGAs configuration clock. With BUSY Low and include both XCFxxP and XCFxxS PROMs.
CF High, after CE and OE are enabled, data is available on
the PROMs DATA (D0-D7) pins. New data is available a
DS123 (v2.19) June 6, 2016 www.xilinx.com
Product Specification 2