SLG46110V-SKT Silego

SLG46110 GreenPAK Programmable Mixed Signal Matrix Features Pin Configuration Logic & Mixed Signal Circuits Highly Versatile Macrocells 1.8 V (5%) to 5 V (10%) Supply Operating Temperature Range: -40C to 85C RoHS Compliant / Halogen-Free 12 10 11 1 Pb-Free 12-pin STQFN: 1.6 x 1.6 x 0.55 mm, 0.4 mm pitch VDD GPIO 9 2 GPIO GPI Applications 8 3 GPIO GPIO 5 6 7 Personal Computers and Servers 4 GND GPIO PC Peripherals Consumer Electronics Data Communications Equipment Handheld and Portable Electronics STQFN-12 (Top View) Block Diagram Pin 12 Pin 11 GPIO NC Look Up Tables (LUTs) Counters/Delay Generators Pin 1 Pin 10 VDD GPIO 2-bit 2-bit ACMP0 CNT0 CNT1 CNT3 LUT2 2 LUT2 3 3-bit 3-bit LUT3 2 LUT3 3 Pin 2 Pin 9 Additional GPI GPIO Combination Functions ACMP1 FILTER 0/Prog. Delay Combination Function Macrocells Pin 3 Pin 8 GPIO 2-bit 2-bit 4-bit GPIO LUT2 0 LUT2 1 LUT4 0 RC Oscillator Vref or DFF0 or DFF1 or CNT2 3-bit 3bit 3-bit LUT3 4 or LUT3 0 LUT3 1 Pin 4 Pin 7 Pipe Delay Bandgap POR or DFF2 or DFF3 GPIO GND Pin 5 Pin 6 NC GPIO 2019 Dialog Semiconductor Revised October 29, 2019 Revision 1.08 NC GPIO GPIO NCSLG46110 1.0 Overview The SLG46110 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46110. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following: Two Analog Comparators (ACMP) Voltage References (Vref) Four Combinatorial Look Up Tables (LUTs) Two 2-bit LUTs Two 3-bit LUTs Seven Combination Function Macrocell Two Selectable DFF/Latch or 2-bit LUTs Two Selectable DFF/Latch or 3-bit LUTs One Selectable Pipe Delay or 3-bit LUT Pipe Delay 8 stage / 2 output One Selectable Counter/Delay or 4-bit LUT One Programmable Delay / Deglitch Filter Three Counter / Delay Generators (CNT/DLY) Three 8-bit counter/delays with external clock/reset Four D Flip-Flop / Latches (DFF) (Part of Combination Function Macrocell) Pipe Delay 8 stage/2 output (Part of Combination Function Macrocell) One Bandgap RC Oscillator (RC OSC) Power On Reset (POR) 2019 Dialog Semiconductor Page 1 of 81 Revision 1.08