SLG59H1120V SLG59H1120V A 12 V, 18 m, 5 A Integrated Power Switch with V Lockout Select and MOSFET Current Monitor Output IN General Description Pin Configuration The SLG59H1120V is a high-performance, self-powered RSET IOUT 18 m NMOS power switch designed for all 4.5 V to 12 V power rails up to 5 A. Using a proprietary MOSFET design, the 1 ON 16 CAP 18 17 SLG59H1120V achieves a stable 18 m RDS across a ON wide input voltage range. In combining novel FET design and SEL0 2 15 FAULT copper pillar interconnects, the SLG59H1120V package also GND 3 14 exhibits a low thermal resistance for high-current operation. SEL1 Designed to operate over a -40 C to 85 C range, the VIN 4 13 VOUT SLG59H1120V is available in a low thermal resistance, RoHS-compliant, 1.6 x 3.0 mm STQFN package. VIN 5 12 VOUT VIN 6 11 VOUT Features Wide Operating Input Voltage: 4.5 V to 13.2 V 10 VIN 7 89 VOUT Maximum Continuous Current: 5 A Automatic nFET SOA Protection VIN VOUT High-performance MOSFET Switch 18-pin STQFN Low RDS : 18 m at V = 12 V ON IN 1.6 x 3.0 mm, 0.40mm pitch Low RDS /V : < 0.05 m/V ON IN Low RDS /T: < 0.06 m/C ON (Top View) 3-Level, Pin-selectable V Overvoltage Lockout IN Capacitor-adjustable Inrush Current Control Two stage Current Limit Protection: Applications Resistor-adjustable Active Current Limit Enterprise Computing & Telecom Equipment Internal Short-circuit Current limit 5 V and 12 V Point-of-Load Power Distribution Open Drain FAULT Signaling PCI/PCIe Adapter Cards MOSFET Current Analog Output Monitor: 10 A/A General-purpose High-voltage, Power-Rail Switching Fast 4 k Output Discharge Multifunction Printers Pb-Free / Halogen-Free / RoHS Compliant Packaging Fan Motor Control Block Diagram and a 12 V / 3 A Typical Application Circuit C LOAD 22 F 12 V 10% 3 A VIN (clamped at 13.2 V) C = C + C + C IN 1 2 3 VOUT 3 V FS - Connect Charge IOUT to System ADC C C C 1 2 3 Pump 47 F 1 to 0.1 F 22 F R C IOUT IOUT 84.5 k 0.18 nF Linear Ramp Control CAP C SLEW V RSET LOGIC R CAP 10 nF 400 k R SET V R LOGIC PU2 State Machine 30.1 k 100 k (CL/SC Detection and R PU1 10 k Over Temperature Connect to SEL0 VIN OVLO FAULT Protection) System GPI 14.4V SEL1 ON ON CMOS Input Discharge OFF GND Datasheet Revision 1.02 12-Dec-2018 Page 1 of 28 2018 Dialog Semiconductor CFR0011-120-01SLG59H1120V A 12 V, 18 m, 5 A Integrated Power Switch with V Lockout Select and MOSFET Current Monitor Output IN Pin Description Pin Pin Name Type Pin Description A low-to-high transition on this pin initiates the operation of the SLG59H1120Vs state machine. ON is an asserted HIGH, level-sensitive CMOS input with ON V < 0.3 V and ON V > 0.9 V. IL IH 1 ON Input As the ON pin input circuit does not have an internal pull-down resistor, connect this pin to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller do not allow this pin to be open-circuited. As level-sensitive, CMOS inputs with V < 0.3 V and V > 1.65 V, the SEL0 (LSB) and the IL IH SEL1 (MSB) pins select one of three V overvoltage lockout thresholds. Please see the IN Applications Section for additional information and the Electrical Characteristics table for the 2 SEL0 Input V overvoltage thresholds. A logic LOW on either pin is achieved by connecting the pin of IN interest to GND a logic HIGH on either pin is achieved by connecting a 10 k external resistor from the pin in question to the systems local logic supply. Pin 3 is the main ground connection for the SLG59H1120Vs internal charge pump, its gate 3GND GND driver and current-limit circuits as well as its internal state machine. Therefore, use a short, stout connection from Pin 3 to the systems analog or power plane. VIN supplies the power for the operation of the SLG59H1120V, its internal control circuitry, and the drain terminal of the nFET power switch. With 5 pins fused together at VIN, connect a 47 F 4-8 VIN MOSFET (or larger) low-ESR capacitor from this pin to ground. Capacitors used at VIN should be rated at 50 V or higher. Source terminal of n-channel MOSFET (5 pins fused for VOUT). Connect a 22 F (or larger) 9-13 VOUT MOSFET low-ESR capacitor from this pin to ground. Capacitors used at VOUT should be rated at 50 V or higher. 14 SEL1 Input Please see SEL0 Pin Description above An open drain output, FAULT is asserted within TFAULT when a V overvoltage, a LOW IN current-limit, or an over-temperature condition is detected. FAULT is deasserted within 15 FAULT Output TFAULT when the fault condition is removed. Connect an 100 k external resistor from the HIGH FAULT pin to local system logic supply. A low-ESR, stable dielectric, ceramic surface-mount capacitor connected from CAP pin to GND sets the V slew rate and overall turn-on time of the SLG59H1120V. For best performance, OUT the range for C values are 10 nF C 20 nF please see typical characteristics for SLEW SLEW 16 CAP Output additional information. Capacitors used at the CAP pin should be rated at 10 V or higher. Please consult Applications Section on how to select C based on V slew rate and loading SLEW OUT conditions. IOUT is the SLG59H1120Vs power MOSFET load current monitor output. As an analog current output, this signal when applied to a ground-reference resistor generates a voltage proportional to the current through the n-channel MOSFET. The I transfer characteristic is typically OUT 17 IOUT Output 10 A/A with a voltage compliance range of 0.5 V V 4 V. Optimal I linearity is IOUT OUT exhibited for 0.5 A I 5 A. In addition, it is recommended to bypass the IOUT pin to GND DS with a 0.18 nF capacitor. A 1%-tolerance, metal-film resistor between 18 k and 91 k sets the SLG59H1120Vs active 18 RSET Input current limit. A 91 k resistor sets the SLG59H1120Vs active current limit to 1 A and a 18 k resistor sets the active current limit to 5 A. Datasheet Revision 1.02 12-Dec-2018 Page 2 of 28 2018 Dialog Semiconductor CFR0011-120-01