SLG59M1649V SLG59M1649V An Ultra-small, Low-power 23 m, 4 A, P-Channel Integrated Power Switch with Reverse-Current Blocking General Description Pin Configuration The SLG59M1649V is a self-powered, high-performance, 23 mpFET integrated power switch designed for 1.5 V to 1 8 VIN 5.5 V power rail applications up to 4 A. When enabled, internal VOUT reverse-current protection will quickly open the switch in the event of a reverse-voltage condition is detected 2 7 ON GND (a V + 50 mV > V condition opens the switch). Upon the OUT IN detection of a reverse condition, an open-drain FAULT output FAULT ON 3 6 is asserted. In the event the V voltage is too low, the power IN switch also contains an internal V threshold monitor to IN(UVLO) keep or to turn the switch OFF. VOUT VIN 4 5 Designed to operate over a -40C to 85C range, the 8-pin STDFN SLG59M1649V is available in a RoHS-compliant, ultra-small 1.0 x 1.6 mm STDFN package. (Top View) Features Applications Steady-state Operating Current: Up to 4 A Power-Rail Switching: Low Typical RDS : ON Notebook/Laptop/Tablet PCs 23 m at V = 5 V IN Smartphones/Wireless Handsets 31 m at V = 2.5 V IN High-definition Digital Cameras 42 m at V = 1.5 V IN Set-top Boxes Operating Voltage: 1.5 V to 5.5 V Point of Sales Pins Reverse-voltage Detection when ON or OFF GPS Navigation Devices Internal Gate Driver and V Discharge OUT Open-drain FAULT Signaling Operating temperature range: -40 C to 85C Low , 8-pin 1.0 mm x 1.6 mm STDFN Packaging JA Pb-Free / Halogen-Free / RoHS compliant packaging Block Diagram I LOAD Reverse Voltage Detection VOUT VIN FAULT Logic Control SW Closed Discharge ON CMOS Input SW Open GND Datasheet Revision 1.01 12-Dec-2018 Page 1 of 16 2018 Dialog Semiconductor CFR0011-120-01SLG59M1649V An Ultra-small, Low-power 23 m, 4 A, P-Channel Integrated Power Switch with Reverse-Current Blocking Pin Description Pin Pin Name Type Pin Description threshold, VIN supplies the power for the operation of the With an internal 1.4 V V IN(UVLO) 1, 4 VIN Power/Input power switch, the internal control circuitry, and the source terminal of pFET. Bypass the VIN pin to GND with a 2.2 F (or larger), low-ESR capacitor. A low-to-high transition on this pin initiates the operation of the power switch. ON is an asserted-HIGH, level-sensitive CMOS input with ON V < 0.3 V and ON V > 1 V. As the IL IH 2, 3 ON Input ON input circuitry does not have an internal pull-down resistor, connect the ON pin directly to a GPIO controller do not allow this pin to be open circuited. 5, 8 VOUT Output Output and drain terminal of MOSFET. An open drain output, FAULT is asserted within TFAULT when a LOW (V + V > V ) condition is detected. The FAULT output is deasserted within OUT REVERSE IN 6FAULT Output TFAULT when the fault condition is removed. Connect an external 10 k resistor from HIGH the FAULT pin to the systems local logic supply. 7 GND GND Ground connection. Connect this pin to system analog or power ground plane. Ordering Information Part Number Type Production Flow SLG59M1649V STDFN 8L Industrial, -40 C to 85 C SLG59M1649VTR STDFN 8L (Tape and Reel) Industrial, -40 C to 85 C Datasheet Revision 1.01 12-Dec-2018 Page 2 of 16 2018 Dialog Semiconductor CFR0011-120-01