Si4330-B1-FM Silicon Labs

Si4330-B1 Si4330 ISM RECEIVER Features Frequency Range = 240960 MHz Programmable GPIOs Sensitivity = 121 dBm Embedded antenna diversity Low Power Consumption algorithm 18.5 mA receive Configurable packet handler Data Rate = 0.123 to 256 kbps Preamble detector FSK, GFSK, and OOK modulation RX 64 byte FIFO Power Supply = 1.8 to 3.6 V Low battery detector Ultra low power shutdown mode Temperature sensor and 8-bit ADC Digital RSSI 40 to +85 C temperature range Wake-up timer Integrated voltage regulators Ordering Information: Frequency hopping capability Auto-frequency calibration (AFC) See page 63. On-chip crystal tuning Clear channel assessment 20-Pin QFN package Programmable RX BW 2.6620 kHz Low BOM Pin Assignments Programmable packet handler Power-on-reset (POR) Si4330 Applications Remote control Remote meter reading 20 19 18 17 VDD RF 1 16 Home security & alarm Remote keyless entry NC 2 15 SCLK Telemetry Home automation Personal data logging Industrial control RXp 3 14 SDI GND Toy control Sensor networks PAD RXn 4 13 SDO Tire pressure monitoring Health monitors NC 5 12 VDD DIG Wireless PC peripherals Tag readers 6 11 NC 7 8 9 10 Description Silicon Laboratories Si4330 is a highly integrated, single chip wireless ISM receiver. The high-performance EZRadioPRO family includes a complete line of transmitters, receivers, and transceivers allowing the RF system designer to Patents pending choose the optimal wireless part for their application. The Si4330 offers advanced radio features including continuous frequency coverage from 240960MHz. The Si4330s high level of integration offers reduced BOM cost while simplifying the overall system design. The extremely low receive sensitivity (121dBm) ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte RX FIFO, automatic packet handling, and preamble detection reduce overall current consumption and allow the use of a lower-cost system MCU. An integrated temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The Si4330s digital receive architecture features a high-performance ADC and DSP based modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer s system design and reducing time to market. Rev 1.0 12/09 Copyright 2009 by Silicon Laboratories Si4330 Not Recommended for New Designs ANT1 SDN GPIO 0 GPIO 1 XIN GPIO 2 XOUT VR DIG nIRQ nSELSi4330-B1 Functional Block Diagram 2 Preliminary Rev. 0.1 Not Recommended for New Designs