Si4420 Universal ISM Si4420 Band FSK Transceiver PIN ASSIGNMENT DESCRIPTION SDI nINT / VDI Silicon Labs Si4420 is a single chip, low power, multi-channel FSK SCK ARSSI transceiver designed for use in applications requiring FCC or ETSI nSEL VDD conformance for unlicensed use in the 315, 433, 868 and 915 MHz SDO RF1 TM nIRQ RF2 bands. The Si4420 transceiver is a part of Silicon Labs EZRadio product FSK / DATA / nFFS VSS line, which produces a flexible, low cost, and highly integrated solution that DCLK / CFIL / FFIT nRES does not require production alignments. The chip is a complete analog RF CLK XTL / REF and baseband transceiver including a multi-band PLL synthesizer with PA, LNA, I/Q down converter mixers, baseband filters and amplifiers, and an Rev C and later I/Q demodulator. All required RF functions are integrated. Only an external crystal and bypass filtering are needed for operation. This document refers to Si4420-IC Rev D1. The Si4420 features a completely integrated PLL for easy RF design, and See www.silabs.com/integration for any applicable its rapid settling time allows for fast frequency-hopping, bypassing errata. See back page for ordering information. multipath fading and interference to achieve robust wireless links. The PLLs high resolution allows the usage of multiple channels in any of the FEATURES bands. The receiver baseband bandwidth (BW) is programmable to Fully integrated (low BOM, easy design-in) accommodate various deviation, data rate and crystal tolerance No alignment required in production requirements. The transceiver employs the Zero-IF approach with I/Q Fast-settling, programmable, high-resolution PLL synthesizer demodulation. Consequently, no external components (except crystal and Fast frequency-hopping capability decoupling) are needed in most applications. High bit rate (up to 115.2 kbps in digital mode and 256 kbps The Si4420 dramatically reduces the load on the microcontroller with the in analog mode) Direct differential antenna input/output integrated digital data processing features: data filtering, clock recovery, Integrated power amplifier data pattern recognition, integrated FIFO and TX data register. The Programmable TX frequency deviation (15 to 240 KHz) automatic frequency control (AFC) feature allows the use of a low accuracy Programmable RX baseband bandwidth (67 to 400 kHz) (low cost) crystal. To minimize the system cost, the Si4420 can provide a Analog and digital RSSI outputs clock signal for the microcontroller, avoiding the need for two crystals. Automatic frequency control (AFC) For low power applications, the Si4420 supports low duty cycle operation Data quality detection (DQD) Internal data filtering and clock recovery based on the internal wake-up timer. RX synchron pattern recognition SPI compatible serial control interface FUNCTIONAL BLOCK DIAGRAM Clock and reset signals for microcontroller 16 bit RX Data FIFO Two 8 bit TX data registers MIX I DCLK / AMP OC 7 CFIL / Low power duty cycle mode FFIT / clk RF1 13 I/Q Data Filt LNA Self cal. data FSK / CLK Rec DEMOD 6 Standard 10 MHz crystal reference DATA / RF2 12 MIX nFFS Q AMP OC Wake-up timer PA FIFO 2.2 to 5.4 V supply voltage Low power consumption PLL & I/Q VCO RSSI COMP DQD AFC with cal. Low standby current (0.3 A) RF Parts BB Amp/Filt./Limiter Data processing units Compact 16 pin TSSOP package WTM CLK div Xosc LBD Controller Bias TYPICAL APPLICATIONS with cal. Low Power parts Remote control Home security and alarm 8 9 15 1 2 3 4 5 10 16 11 14 CLK XTL / ARSSI SDI SCK nSEL SDO nIRQ nRES nINT / VSS VDD Wireless keyboard/mouse and other PC peripherals REF VDI Toy controls Remote keyless entry Tire pressure monitoring Telemetry Remote automatic meter reading 1 Si4420-DS Rev 1.7r 0308 www.silabs.com Si4420 DETAILED FEATURE-LEVEL DESCRIPTION The Si4420 FSK transceiver is designed to cover the unlicensed frequency bands at 315, 433, 868 and 915 MHz. The devices facilitate compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application. The Si4420 incorporates a fully integrated multi-band PLL synthesizer, PA with antenna tuning, an LNA with switchable gain, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator followed by a data filter. PLL The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip Data Filtering and Clock Recovery crystal-controlled reference oscillator. The PLLs high resolution allows the usage of multiple channels in any of the bands. Output data filtering can be completed by an external capacitor or by using digital filtering according to the final application. The RF VCO in the PLL performs automatic calibration, which requires only a few microseconds. Calibration always occurs Analog operation: The filter is an RC type low-pass filter followed when the synthesizer starts. If temperature or supply voltage by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are changes significantly or operational band has changed, VCO integrated on the chip. An (external) capacitor can be chosen recalibration is recommended.. Recalibration can be initiated at according to the actual bit rate. In this mode, the receiver can any time by switching the synthesizer off and back on again. handle up to 256 kbps data rate. The FIFO can not be used in this mode and clock is not provided for the demodulated data. RF Power Amplifier (PA) Digital operation: A digital filter is used with a clock frequency at The power amplifier has an open-collector differential output and 29 times the bit rate. In this mode there is a clock recovery can directly drive a loop antenna with a programmable output circuit (CR), which can provide synchronized clock to the data. power level. An automatic antenna tuning circuit is built in to Using this clock the received data can fill a FIFO. The CR has avoid costly trimming procedures and the so-called hand effect. three operation modes: fast, slow, and automatic. In slow mode, its noise immunity is very high, but it has slower settling time and LNA requires more accurate data timing than in fast mode. In The LNA has 250 Ohm input impedance, which functions well automatic mode the CR automatically changes between fast and with the proposed antennas (see: Application Notes available slow mode. The CR starts in fast mode, then after locking it from www.silabs.com/integration) automatically switches to slow mode. If the RF input of the chip is connected to 50 Ohm devices, an (Only the digital data filter and the clock recovery use the bit rate external matching circuit is required to provide the correct clock. For analog operation, there is no need for setting the matching and to minimize the noise figure of the receiver. correct bit rate.) The LNA gain can be selected (0, 6, 14, 20 dB relative to the highest gain) according to RF signal strength. It can be useful in an environment with strong interferers. Baseband Filters The receiver bandwidth is selectable by programming the bandwidth (BW) of the baseband filters. This allows setting up the receiver according to the characteristics of the signal to be received. An appropriate bandwidth can be chosen to accommodate various FSK deviation, data rate and crystal tolerance requirements. The filter structure is 7th order Butterworth low- pass with 40 dB suppression at 2*BW frequency. Offset cancellation is done by using a high-pass filter with a cut-off frequency below 7 kHz. 2