RF Agile Transceiver Data Sheet AD9363 FEATURES FUNCTIONAL BLOCK DIAGRAM RX1B P, Radio frequency (RF) 2 2 transceiver with integrated 12-bit RX1B N AD9363 DACs and ADCs RX1A P, ADC RX1A N Wide bandwidth: 325 MHz to 3.8 GHz RX1C P, Supports time division duplex (TDD) and frequency division RX1C N RX2B P, duplex (FDD) operation RX2B N P0 D11/ Tunable channel bandwidth (BW): up to 20 MHz RX2A P, TX D5 x TO P0 D0/ ADC RX2A N TX D0 x Receivers: 6 differential or 12 single-ended inputs RX2C P, RX LO RX2C N Superior receiver sensitivity with a noise figure: 3 dB Receive (Rx) gain control TX MON1 TX LO P1 D11/ Real-time monitor and control signals for manual gain TX1A P, DAC RX D5 x TO P1 D0/ TX1A N RX D0 x Independent automatic gain control (AGC) TX1B P, TX1B N Dual transmitters: 4 differential outputs Highly linear broadband transmitter TX MON2 TX2A P, Transmit (Tx) error vector magnitude (EVM): 34 dB DAC TX2A N Tx noise: 157 dBm/Hz noise floor TX2B P, RADIO GGPOPO TX2B N SWITCHING Tx monitor: 66 dB dynamic range with 1 dB accuracy SPI Integrated fractional N synthesizers CTRL PLLs CLK OUT CTRL 2.4 Hz local oscillator (LO) step size AUXADC AUXDACx XTALN CMOS/LVDS digital interface NOTES 1. SPI, CTRL, P0 D11/TX D5 x TO P0 D0/TX D0 x, P1 D11/ APPLICATIONS RX D5 x TO P1 D0/RX D0 x, AND RADIO SWITCHING CONTAIN MULTIPLE PINS. 3G enterprise femtocell base stations Figure 1. 4G femtocell base stations Wireless video transmission GENERAL DESCRIPTION The AD9363 is a high performance, highly integrated RF agile sample rate. transceiver designed for use in 3G and 4G femtocell applications. The transmitters use a direct conversion architecture that achieves Its programmability and wideband capability make it ideal for a high modulation accuracy with ultralow noise. This transmitter broad range of transceiver applications. The device combines an design produces a best-in-class Tx EVM of 34 dB, allowing RF front end with a flexible mixed-signal baseband section and significant system margin for the external power amplifier (PA) integrated frequency synthesizers, simplifying design-in by selection. The on-board Tx power monitor can be used as a providing a configurable digital interface to a processor. The power detector, enabling highly accurate Tx power AD9363 operates in the 325 MHz to 3.8 GHz range, covering measurements. most licensed and unlicensed bands. Channel bandwidths from The fully integrated phase-locked loops (PLLs) provide low less than 200 kHz to 20 MHz are supported. power fractional N frequency synthesis for all receive and The two independent direct conversion receivers have state-of- transmit channels. Channel isolation, demanded by FDD the-art noise figure and linearity. Each Rx subsystem includes systems, is integrated into the design. All voltage controlled independent automatic gain control (AGC), dc offset correction, oscillators (VCOs) and loop filter components are integrated. quadrature correction, and digital filtering, thereby eliminating The core of the AD9363 can be powered directly from a 1.3 V the need for these functions in the digital baseband. The AD9363 regulator. The IC is controlled via a standard 4-wire serial port also has flexible manual gain modes that can be externally and four real-time I/O control pins. Comprehensive power-down controlled. Two high dynamic range ADCs per channel digitize modes are included to minimize power consumption during the received I and Q signals and pass them through configurable normal use. The AD9363 is packaged in a 10 mm 10 mm, decimation filters and 128-tap finite impulse response (FIR) 144-ball chip scale package ball grid array (CSP BGA). filters to produce a 12-bit output signal at the appropriate Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADC DAC DAC DATA INTERFACE 10558-001AD9363 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 2.4 GHz Frequency Band .......................................................... 24 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 28 Functional Block Diagram .............................................................. 1 General......................................................................................... 28 General Description ......................................................................... 1 Receiver........................................................................................ 28 Revision History ............................................................................... 2 Transmitter .................................................................................. 28 Specifications ..................................................................................... 3 Clock Input Options .................................................................. 28 Current ConsumptionVDD INTERFACE........................... 8 Synthesizers ................................................................................. 28 Current ConsumptionVDDD1P3 DIG and VDDAx Digital Data Interface................................................................. 29 (Combination of All 1.3 V Supplies) ....................................... 11 Enable State Machine ................................................................. 29 Absolute Maximum Ratings ..................................................... 15 SPI Interface ................................................................................ 30 Reflow Profile .............................................................................. 15 Control Pins ................................................................................ 30 Thermal Resistance .................................................................... 15 GPO Pins (GPO 3 to GPO 0) ................................................. 30 ESD Caution ................................................................................ 15 Auxiliary Converters .................................................................. 30 Pin Configuration and Function Descriptions ........................... 16 Packaging and Ordering Information ......................................... 32 Typical Performance Characteristics ........................................... 20 Outline Dimensions ................................................................... 32 800 MHz Frequency Band ......................................................... 20 Ordering Guide .......................................................................... 32 REVISION HISTORY 11/2016Revision D: Initial Version Rev. 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