Si5319 ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features Generates any frequency from 2 kHz to 945 MHz and Support for ITU G.709 and custom OTN FEC ratios (e.g. select frequencies to 1.4 GHz from an input frequency of 255/238, 255/237, 255/236) 2 kHz to 710 MHz Supports various frequency translations for Synchronous Ultra-low jitter clock output with jitter generation as low as Ethernet 0.3 ps rms (50 kHz80 MHz) LOL, LOS alarm outputs 2 Integrated loop filter with selectable loop bandwidth I C or SPI programmable (60 Hz to 8.4 kHz) On-chip voltage regulator for 1.8 V 5%, 2.5 V 10% or Meets OC-192 GR-253-CORE jitter specifications 3.3 V 10% operation Clock or crystal input with manual clock selection Small size: 6 x 6 mm 36-lead QFN Selectable clock output signal format Pb-free, ROHS compliant (LVPECL, LVDS, CML, CMOS) Applications 10G/40G/100G OTN line cards Wireless basestations SONET/SDH OC-48/STM-16 and OC-192/STM-64 Data converter clocking line cards DSLAM/MSANs GbE/10GbE, 1/2/4/8/10GFC line cards Test and measurement ITU G.709 and custom FEC line cards Broadcast video Synchronous Ethernet Discrete PLL replacement Optical modules Description The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance. The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for free-running clock generation. The device provides virtually any frequency translation combination across this operating range. The Si5319 input 2 clock frequency and clock multiplication ratio are programmable through an I C or SPI interface. The Si5319 is based on Silicon Laboratories third-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Rev. 1.0 12/10 Copyright 2010 by Silicon Laboratories Si5319 Si5319 2 Rev. 1.0