Si5324 ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR Features Generates any frequency from Freerun, Digital Hold operation 2 kHz to 945 MHz and select Configurable signal format per frequencies to 1.4 GHz from an output (LVPECL, LVDS, CML, input frequency of 2 kHz to CMOS) 710 MHz Support for ITU G.709 and custom Ultra-low jitter clock outputs as low FEC ratios (255/238, 255/237, as 290 fs rms (12 kHz20 MHz), 255/236, 239/237, 66/64, 239/238, 320 fs rms (50 kHz80 MHz) 15/14, 253/221, 255/238) Integrated loop filter with LOL, LOS, FOS alarm outputs 2 selectable loop bandwidth I C or SPI programmable (4 525 Hz) On-chip voltage regulator with high Meets ITU-T G.8251 and Telcordia PSNR Ordering Information: GR-253-CORE jitter specification Single supply 1.8 5%, 2.5 10%, See page 64. Hitless input clock switching with or 3.3 V 10% phase build-out Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS-compliant Pin Assignments Applications Broadcast video 3G/HD/SD-SDI, 1/2/4/8/10G Fibre Channel line Genlock cards 36 35 34 33 32 31 30 29 28 Packet Optical Transport Systems GbE/10/40/100G Synchronous RST 1 27 SDI NC 2 26 A2 SS (P-OTS), MSPP Ethernet (LAN/WAN) INT C1B 3 25 A1 OTN/OTU-1/2/3/4 Asynchronous Data converter clocking C2B 4 24 A0 GND Demapping (Gapped Clock) Wireless base stations VDD 5 23 SDA SDO Pad XA 6 22 SCL SONET OC-48/192/768, Test and measurement XB 7 21 CS CA SDH/STM-16/64/256 line cards GND 8 20 GND NC 9 19 GND 10 11 12 13 14 15 16 17 18 Description The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier for applications requiring sub 1 ps jitter performance with loop bandwidths between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The Si5324 can also use its external reference as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5324 input clock frequency and clock multiplication 2 ratio are programmable via an I C or SPI interface. The Si5324 is based on Skyworks Solutions 3rd-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. The Si5324 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 23, 2021 VDD CMODE RATE0 CKOUT2+ CKIN2+ CKOUT2 CKIN2 NC NC VDD RATE1 GND CKIN1+ NC CKIN1 CKOUT1 LOL CKOUT1+Si5324 Functional Block Diagram Xtal or Refclock CKIN1 N31 NC1 LS CKOUT1 CKIN2 N32 DSPLL N1 HS CKOUT2 NC2 LS Xtal/Refclock N2 Loss of Signal/ VDD (1.8, 2.5, or 3.3 V) Frequency Offset Control Signal Detect GND Loss of Lock 2 I C/SPI Port Clock Select Device Interrupt Skew Adjust Rate Select 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 23, 2021