Si5345/44/42 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER Features Generates any combination of Optional zero delay mode output frequencies from any input Fastlock feature: <200 ms lock time frequencies Glitchless on the fly output Input frequency range: frequency changes Differential: 8 kHz to 750 MHz DCO mode: as low as 0.001 ppb LVCMOS: 8 kHz to 250 MHz steps. Output frequency range: Core voltage Differential: up to 800 MHz V : 1.8 V 5% DD LVCMOS: up to 250 MHz V : 3.3 V 5% DDA Jitter performance: Independent output supply pins: <100 fs typ (12 kHz20 MHz) 3.3V, 2.5V, or 1.8V Programmable jitter attenuation Output-output skew: <100 ps Ordering Information: bandwidth: 0.1 Hz to 4 kHz 2 See section 7 Serial interface: I C or SPI Meets G.8262 EEC Opt 1, 2 (SyncE) In-circuit programmable with Highly configurable outputs non-volatile OTP memory compatible with LVDS, LVPECL, TM Pin Assignments ClockBuilder Pro software LVCMOS, HCSL, or programmable simplifies device configuration voltage swing and common mode Si5345 Top View Si5345: 4 input, 10 output, 64 QFN Status monitoring (LOS, OOF, LOL) Si5344: 4 input, 4 output, 44 QFN Hitless input clock switching: Si5342: 4 input, 2 output, 44 QFN automatic or manual IN1 1 48 FINC 2 47 IN1 LOL IN SEL0 3 46 VDD Temperature range: 40 to +85 C Locks to gapped clock inputs IN SEL1 4 45 OUT6 5 44 RSVD OUT6 Pb-free, RoHS-6 compliant Automatic free-run and holdover RST 6 43 VDDO6 X1 7 42 OUT5 41 XA 8 GND OUT5 modes XB 9 40 VDDO5 Pad X2 10 39 I2C SEL 38 OE 11 OUT4 INTR 12 37 OUT4 Applications VDDA 13 36 VDDO4 35 IN2 14 OUT3 IN2 15 34 OUT3 SCLK 16 33 VDDO3 OTN Muxponders and Carrier Ethernet switches Transponders SONET/SDH Line Cards 10/40/100G network line cards Broadcast video Si5344 44QFN Top View GbE/10GbE/100GbE Synchronous Test and measurement Ethernet 1 33 IN1 INTR IN1 2 32 VDD Description IN SEL0 3 31 OUT2 4 30 X1 OUT2 5 29 VDDO2 XA GND XB 6 28 LOS XAXB Pad These jitter attenuating clock multipliers combine fourth-generation DSPLL and 7 27 LOL X2 VDDA 8 26 VDDS VDDA 9 25 OUT1 MultiSynth technologies to enable any-frequency clock generation and jitter 10 24 IN2 OUT1 11 23 VDDO1 IN2 attenuation for applications that require the highest level of jitter performance. These devices are programmable via a serial interface with in-circuit programmable non-volatile memory (NVM) so that they always power up with a Si5342 44QFN known frequency configuration. They support free-run, synchronous, and Top View holdover modes of operation, and offer both automatic and manual input clock switching. The loop filter is fully integrated on-chip eliminating the risk of potential IN1 1 33 INTR noise coupling associated with discrete solutions. Further, the jitter attenuation IN1 2 32 VDD IN SEL0 3 31 LOS1 X1 4 30 LOS0 bandwidth is digitally programmable providing jitter performance optimization at XA 5 29 VDDS GND 6 28 LOS XAXB XB Pad the application level. Programming the Si5345/44/42 is made easy with Silicon X2 7 27 LOL VDDA 8 26 VDDS 9 25 OUT1 Labs ClockBuilderPro software. Factory preprogrammed devices are also VDDA 10 24 OUT1 IN2 IN2 11 23 VDDO1 available. Preliminary Rev. 0.9 7/14 Copyright 2014 by Silicon Laboratories Si5345/44/42 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. A1/SDO 17 64 IN0 SDA/SDIO 18 63 IN0 A0/CS 19 62 OE 12 44 IN0 12 44 IN3/FB IN OE IN0 13 43 RSVD 20 61 IN3/FB IN SDA/SDIO IN0 SDA/SDIO 13 43 IN0 SCLK 14 42 14 RSVD 21 60 VDD IN3/FB IN SCLK 42 IN3/FB IN 22 59 A1/SDO 15 41 IN3/FB IN 15 41 VDDO0 OUT9 A1/SDO IN3/FB IN 16 OUT0 23 58 OUT9 A0/CS 40 VDD A0/CS 16 40 VDD 17 39 OUT0 24 57 VDDO9 RST VDD RST 17 39 VDD 25 56 VDDO0 18 38 I2C SEL 18 38 FDEC RSVD VDDO0 I2C SEL 26 55 OUT0 19 37 IN SEL1 OUT0 19 37 IN SEL1 VDDO1 RSVD 20 36 LOS3 OUT1 27 54 OUT8 OUT0 OUT0 20 36 OUT3 VDD 21 35 LOS2 VDD 21 35 OUT3 OUT1 28 53 OUT8 34 VDDO2 29 52 VDDO8 NC 22 VDDS NC 22 34 VDDO3 OUT2 30 51 OUT7 OUT2 31 50 OUT7 VDD 32 49 VDDO7Si5345 Si5344 Si5342 Si5345/44/42 Functional Block Diagram XTAL XB Si5345/44/42 XA IN SEL OSC IN0 FRAC FRAC IN1 DSPLL FRAC IN2 IN3/ FRAC FB IN Optional External Feedback Multi INT OUT0 Synth Multi INT OUT1 Synth Multi INT OUT2 Synth Multi INT OUT3 Synth Multi INT OUT4 Synth INT OUT5 NVM INT OUT6 2 I C/SPI INT OUT7 Control/ INT OUT8 Status INT OUT9 2 Preliminary Rev. 0.9