Si5347A/B Si5347C/D Si5346A/B Si5347/46 Rev D Data Sheet Dual/Quad DSPLL Any-Frequency, Any-Output Jitter Attenua- KEY FEATURES tors Four or two independent DSPLLs, any The Si5347 is a high-performance, jitter-attenuating clock multiplier which integrates output frequency from any input frequency four any-frequency DSPLLs for applications that require maximum integration and inde- Ultra-low jitter of 95 fs rms pendent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each Input frequency range: DSPLL has access to any of the four inputs and can provide low jitter clocks on any of External Crystal: 2554 MHz th the device outputs. Based on 4 generation DSPLL technology, these devices provide Differential: 8 kHz to 750 MHz any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL LVCMOS: 8 kHz to 250 MHz supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5347/46 is programmable via a serial interface with Output frequency range: in-circuit programmable non-volatile memory so that it always powers up in a known Differential: 100 Hz to 720 MHz configuration. Programming the Si5347/46 is easy with Silicon Labs ClockBuilder LVCMOS: 100 Hz to 250 MHz Pro software. Factory preprogrammed devices are also available. Status Monitoring Hitless switching Si5347: 4 input, 8 output, 64-QFN 99 mm Applications Si5346: 4 input, 4 output, 44-QFN 77 mm OTN Muxponders and Transponders 10/40/100G network line cards GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262) Carrier Ethernet switches Broadcast video 25-54 MHz XTAL XA XB OSC INT OUT0 INT OUT1 FRAC DSPLL A IN0 INT OUT2 FRAC DSPLL B IN1 INT OUT3 4 Input Clocks INT OUT4 FRAC DSPLL C IN2 INT OUT5 FRAC DSPLL D IN3 INT OUT6 INT OUT7 Status Flags Status Monitor I2C / SPI Control NVM silabs.com Building a more connected world. Rev. 1.1 Table of Contents 1. Feature List................................4 2. Ordering Guide ..............................5 3. Functional Description............................6 3.1 Frequency Configuration ..........................6 3.2 DSPLL Loop Bandwidth...........................6 3.2.1 Fastlock Feature............................6 3.3 Modes of Operation ............................6 3.3.1 Initialization and Reset..........................6 3.3.2 Free-run Mode ............................7 3.3.3 Lock Acquisition Mode..........................7 3.3.4 Locked Mode.............................7 3.3.5 Holdover Mode ............................8 3.4 Digitally-Controlled Oscillator (DCO) Mode ....................8 3.5 External Reference (XA/XB) .........................9 3.6 Inputs (IN0, IN1, IN2, IN3) ..........................10 3.6.1 Input Selection ............................10 3.6.2 Manual Input Selection..........................10 3.6.3 Automatic Input Selection.........................10 3.6.4 Input Configuration and Terminations.....................11 3.6.5 Hitless Input Switching..........................12 3.6.6 Ramped Input Switching .........................12 3.6.7 Glitchless Input Switching.........................12 3.6.8 Synchronizing to Gapped Input Clocks ....................12 3.7 Fault Monitoring .............................13 3.7.1 Input LOS Detection...........................13 3.7.2 XA/XB LOS Detection..........................13 3.7.3 OOF Detection ............................14 3.7.4 LOL Detection.............................15 3.7.5 Interrupt Pin (INTRb) ..........................17 3.8 Outputs ................................17 3.8.1 Output Crosspoint ...........................18 3.8.2 Differential Output Terminations.......................19 3.8.3 LVCMOS Output Terminations .......................19 3.8.4 Output Signal Format ..........................19 3.8.5 Programmable Common Mode Voltage For Differential Outputs............19 3.8.6 LVCMOS Output Impedance Selection ....................20 3.8.7 LVCMOS Output Signal Swing .......................20 3.8.8 LVCMOS Output Polarity.........................20 3.8.9 Output Enable/Disable..........................21 3.8.10 Output Disable During LOL........................21 3.8.11 Output Disable During XAXB LOS .....................21 3.8.12 Output Driver State When Disabled.....................21 3.8.13 Synchronous/Asynchronous Output Disable ..................21 silabs.com Building a more connected world. Rev. 1.1 2