FLASH Si5383/84 Rev D Data Sheet Network Synchronizer Clocks Supporting 1 PPS to 750 MHz KEY FEATURES Inputs One or three independent DSPLLs in a The Si5383/84 combines the industrys smallest footprint and lowest power network single monolithic IC supporting flexible synchronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The SyncE/IEEE 1588 and SETS architectures Si5383/84 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless Input frequency range: communications systems, and data center switches requiring both traditional and packet External crystal: 25-54 MHz based network synchronization. REF clock: 5-250 MHz The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE 1588 Diff clock: 8 kHz - 750 MHz DCO, or a general-purpose PLL for processor/FPGA clocking. The Si5383/84 can also LVCMOS clock: 1 PPS, 8 kHz - 250 be used in legacy SETS systems needing Stratum 3/3E compliance. In addition, locking MHz to a 1 PPS input frequency is available on DSPLL D. The DCO mode provides precise Output frequency range: timing adjustment to 1 part per trillion (ppt). The unique design of the Si5383/84 allows Differential: 1 PPS, 100 Hz - 718.5 MHz the device to accept a TCXO/OCXO reference with a wide frequency range, and the LVCMOS: 1 PPS, 100 Hz - 250 MHz reference clock jitter does not degrade the output performance. The Si5383/84 is config- Ultra-low jitter of less than 150 fs urable via a serial interface and programming the Si5383/84 is easy with ClockBuilder Pro software. Factory pre-programmed devices are also available. Applications Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Options 1 and 2 Telecom Grand Master Clock (T-GM) as defined by ITU-T G.8273.1 Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined by ITU-T G.8273.2 IEEE 1588 (PTP) slave clock synchronization Stratum 3/3E, G.812, G.813, GR-1244, GR-253 network synchronization 1 Hz/1 PPS Clock Multiplier XTAL OCXO/ TCXO REF XB XA REFb OSC Si5383/84 IN4 INT OUT0 DSPLL IN3 D INT OUT1 IN2 FRAC INT OUT2 IN1 DSPLL A FRAC INT OUT3 IN0 FRAC INT OUT4 2 I C INT OUT5 DSPLL C Control/ Status INT OUT6 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 1 Rev. 1.1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 17, 2021 1 Si5384 Si5383Si5383/84 Rev D Data Sheet Feature List 1. Feature List The Si5383/84 highlighted features are listed below. One or three DSPLLs in a single monolithic IC supporting TCXO/OCXO reference input determines DSPLL free-run/hold- flexible SyncE/IEEE 1588 and SETS architectures over accuracy and stability Meets the requirements of: Excellent jitter performance ITU-T G.8273.1 T-GM Programmable loop bandwidth per DSPLL: ITU-T G.8273.2 T-BC, T-TSC 1 PPS inputs: 1 mHz and 10 mHz Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Op- All other inputs: 1 mHz to 4 kHz tions 1 and 2 Highly configurable output drivers: LVDS, LVPECL, LVCMOS, ITU-T G.812 Type III, IV HCSL, CML ITU-T G.813 Option 1 Core voltage: Telcordia GR-1244, GR-253 (Stratum-3/3E) VDD: 1.8 V 5% Each DSPLL generates any output frequency from any input VDDA: 3.3 V 5% frequency Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V Input frequency range: Built-in power supply filtering External crystal: 25 - 54 MHz Status monitoring: REF clock: 5 - 250 MHz LOS, LOL: 1 PPS-750 MHz Diff clock: 8 kHz - 750 MHz OOF: 8 kHz-750 MHz LVCMOS clock: 1 PPS, 8 kHz - 250 MHz 2 I C Serial Interface Output frequency range: TM ClockBuilder Pro software tool simplifies device configura- Differential: 1 PPS, 100 Hz - 718.5 MHz tion LVCMOS: 1 PPS, 100 Hz - 250 MHz 5 input, 7 output, 56-pin LGA Pin or software controllable DCO on each DSPLL with typical Temperature range: 40 to +85 C resolution to 1 ppt/step Pb-free, RoHS-6 compliant Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 Rev. 1.1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 17, 2021 2