SiT1566 2 1.2 mm Power, Low-Jitter, 3 & 5 ppm, 32.768 kHz Super-TCXO 2 Smallest (1.2mm ), Ultra-Low Power, 32.768 kHz MEMS TCXO Features Applications 32.768 kHz 3 and 5 ppm all-inclusive frequency stability Smart watches, health and wellness monitors 2 Worlds smallest TCXO Footprint: 1.2 mm Ultra-accurate RTC reference clock 1.5 x 0.8 mm CSP Smart utility meters, E-meters No external bypass cap required Internet-of-Things (IoT) with BLE Improved stability reduces system power with fewer network timekeeping updates Low integrated phase jitter (IPJ) suitable for multiplying up for portable audio: 2.5 ns RMS Ultra-low power: 4.5 A Operating supply voltage range: 1.62 V to 3.63 V Operating temperature ranges: -20C to +70C, -40C to +85C Pb-free, RoHS and REACH compliant Electrical Specifications Conditions: Min/Max limits are over temperature, Vdd = 1.8V 10%, unless otherwise stated. Typicals are at 25C and Vdd = 1.8V. Table 1. Electrical Characteristics Parameter Symbol Min. Typ. Max. Unit Condition Frequency and Stability Output Frequency Fout 32.768 kHz -3 3 1 Total Frequency Stability F stab ppm All inclusive, 1.62V to 3.63V -5 5 Allan Deviation AD 1e-8 4e-8 1 second averaging time First Year Frequency Aging F aging 1 ppm T = 25C, Vdd = 1.8V A Jitter and Frequency Response Performance Integration bandwidth = 100 Hz to 16.384 kHz. Integrated Phase Jitter Inclusive of 50 mV peak-to-peak sinusoidal noise on Vdd. IPJ 1.8 2.5 ns RMS Noise frequency 100 Hz to 20 MHz. RMS Period Jitter PJRMS 2.5 4 ns RMS 10,000 samples, per JEDEC standard 65B PJ ns Peak-to-Peak Period Jitter 20 35 p-p p-p Dynamic Temperature -0.5 +0.5 ppm/sec Under temp ramp up to 1.5C/sec Frequency Response Supply Voltage and Current Consumption 1.62 1.8 1.98 Operating Supply Voltage Vdd V 1.62 3.63 Supply Current Idd 4.5 5.3 A No load Measured when supply reaches 90% of final Vdd to the first Start-up Time at Power-up t start 300 ms output pulse. Operating Temperature Range -20 70 C C ordering code Operating Temperature Range Op Temp -40 85 C I ordering code LVCMOS Output Output Rise/Fall Time tr, tf 9 20 ns 10 90% Vdd, 15pF load Output Clock Duty Cycle DC 45 55 % Output Voltage High VOH 90% Vdd I = -50 A, 15 pF load OH Output Voltage Low VOL 10% Vdd I = 50 A, 15 pF load OL Note: 1. Relative to 32.768 kHz, includes initial tolerance, over temp stability, Vdd, 20% load variation, hysteresis, board-level underfill (5 ppm only), 2x reflow. Tested with Agilent 53132A frequency counter. Measured with 100 ms gate time for accurate frequency measurement. Rev 1.01 January 16, 2019 www.sitime.com 2 SiT1566 1.2 mm Power, Low-Jitter, 3 & 5 ppm, 32.768 kHz Super-TCXO Table 2. Pin Configuration CSP Package (Top View) Pin Symbol I/O Functionality 1 NC Internal Test Leave Floating. Do not connect to GND. NC 1 4 GND 2 CLK Out OUT Oscillator clock output. LVCMOS compatible logic. 1.8V 10% power supply. Under normal operating conditions, Vdd does not require external bypass/decoupling capacitor(s). 3 Vdd Power Supply SiT1566 includes on-chip filtering capacitors. CLK Out 2 3 Vdd Under extreme noise on the supply, a 10-100 nF low ESR ceramic bypass capacitor may be recommended close to the Vdd pin. 4 GND Power Supply Ground Connect to ground. Figure 1. Pin Assignment Table 3. Absolute Maximum Ratings Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Parameters Test Conditions Value Unit Continuous Power Supply Voltage Range (Vdd) -0.5 to 4.0 V Continuous Maximum Operating Temperature Range 105 C Short Duration Maximum Operating Temperature Range 30 minutes 125 C Human Body Model (HBM) ESD Protection JESD22-A114 2000 V Charge-Device Model (CDM) ESD Protection JESD22-C101 750 V Machine Model (MM) ESD Protection T = 25C 200 V A Latch-up Tolerance JESD78 Compliant Mechanical Shock Resistance Mil 883, Method 2002 20,000 g Mechanical Vibration Resistance Mil 883, Method 2007 70 g 1508 CSP Junction Temperature 150 C Storage Temperature -65 to 150 C System Block Diagram MEMS Resonator GND Control Regulators Vdd Temp Temp-to-Digital NVM Control Prog Prog Ultra-low Sustaining Power NC Divider Driver CLK Out Amp Frac-n PLL Figure 2. SiT1566 Block Diagram Rev 1.01 Page 2 of 9 www.sitime.com