SiT9156 LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet The Smart Timing Choice The Smart Timing Choice Features Applications 0.3 ps RMS phase jitter (random) for 10GbE applications 10GB Ethernet, SONET, SATA, SAS, Fibre Channel, PCI-Express Frequency stability as low as 10 ppm 100% drop-in replacement for quartz and SAW oscillators Telecom, networking, instrumentation, storage, servers Configurable positive frequency shift, +25, +50, or +75 ppm Industry-standard packages: 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mmxmm Industrial and extended commercial temperature ranges Best in class 1-year and 10-year aging Best resilience, up to 40x better than quartz For other frequencies, refer to SiT9121 or 9122 datasheet Electrical Characteristics Parameter and Conditions Symbol Min. Typ. Max. Unit Condition LVPECL and LVDS, Common Electrical Characteristics Supply Voltage Vdd 2.97 3.3 3.63 V 2.25 2.5 2.75 V 2.25 3.63 V Termination schemes in Figures 1 and 2 - XX ordering code Output Frequency Range f 156.25000, 156.253906, MHz 156.253906 MHz, +25 PPM from 156.250000 156.257812, 156.261718, 156.257812 MHz, +50 PPM from 156.250000 156.261718 MHz, +75 PPM from 156.250000 161.132800 Frequency Stability F stab -10 +10 ppm -20 +20 ppm Inclusive of initial tolerance, operating temperature, rated power supply voltage, and load variations -25 +25 ppm -50 +50 ppm First Year Aging F aging1 -2 +2 ppm 25C 10-year Aging F aging10 -5 +5 ppm 25C Operating Temperature Range T use -40 +85 C Industrial -20 +70 C Extended Commercial Input Voltage High VIH 70% Vdd Pin 1, OE or ST Input Voltage Low VIL 30% Vdd Pin 1, OE or ST Input Pull-up Impedance Z in 100 250 k Pin 1, OE logic high or logic low, or ST logic high 2 M Pin 1, ST logic low Start-up Time T start 6 10 ms Measured from the time Vdd reaches its rated minimum value. In Standby mode, measured from the time ST pin crosses Resume Time T resume 6 10 ms 50% threshold. Duty Cycle DC 45 55 % Contact SiTime for tighter duty cycle LVPECL, DC and AC Characteristics Current Consumption Idd 61 69 mA Excluding Load Termination Current, Vdd = 3.3V or 2.5V OE Disable Supply Current I OE 35 mA OE = Low Output Disable Leakage Current I leak 1 A OE = Low Standby Current I std 100 A ST = Low, for all Vdds Maximum Output Current I driver 30 mA Maximum average current drawn from OUT+ or OUT- Output High Voltage VOH Vdd-1.1 Vdd-0.7 V See Figure 1(a) Output Low Voltage VOL Vdd-1.9 Vdd-1.5 V See Figure 1(a) Output Differential Voltage Swing V Swing 1.2 1.6 2.0 V See Figure 1(b) Rise/Fall Time Tr, Tf 300 500 ps 20% to 80%, see Figure 1(a) OE Enable/Disable Time T oe 120 ns f = 156.25 MHz - For other frequencies, T oe = 100ns + 3 period RMS Phase Jitter (random) T phj 0.25 0.3 ps IEEE802.3-2005 10GbE jitter measurement specifications LVDS, DC and AC Characteristics Current Consumption Idd 47 55 mA Excluding Load Termination Current, Vdd = 3.3V or 2.5V OE Disable Supply Current I OE 35 mA OE = Low Differential Output Voltage VOD 250 350 450 mV See Figure 2 SiTime Corporation 990 Almanor Avenue, Sunnyvale, CA 94085 (408) 328-4400 www.sitime.com Rev. 1.06 Revised October 6, 2014SiT9156 LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet The Smart Timing Choice The Smart Timing Choice Electrical Characteristics (continued) Parameter and Conditions Symbol Min. Typ. Max. Unit Condition LVDS, DC and AC Characteristics (continued) Output Disable Leakage CurrentI leak 1 AOE = Low Standby Current I std 100 A ST = Low, for all Vdds VOD Magnitude Change VOD 50 mV See Figure 2 Offset Voltage VOS 1.125 1.2 1.375 V See Figure 2 VOS Magnitude Change VOS 50 mV See Figure 2 Rise/Fall Time Tr, Tf 495 600 ps 20% to 80%, see Figure 2 OE Enable/Disable Time T oe 115 ns f = 156.25 MHz - For other frequencies, T oe = 100ns + 3 period RMS Phase Jitter (random) T phj 0.25 0.3 ps IEEE802.3-2005 10GbE jitter measurement specifications Pin Description Pin Map Functionality Top View H or Open: specified frequency output OE Input L: output is high impedance OE/ST 1 6 VDD 1 H or Open: specified frequency output ST Input L: Device goes to sleep mode. Supply current reduces to I std. NC 2 5 OUT- No Connect Leave it floating or connect to GND for better 2NC NA heat dissipation 3 4 GND OUT+ 3 GND Power VDD Power Supply Ground 4 OUT+ Output Oscillator output 5 OUT- Output Complementary oscillator output 6 VDD Power Power supply voltage Absolute Maximum Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor- mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Parameter Min. Max. Unit Storage Temperature -65 150 C VDD -0.5 4 V Electrostatic Discharge (HBM) 2000 V Soldering Temperature (follow standard Pb free soldering guidelines) 260 C Thermal Consideration JA, 4 Layer Board JC, Bottom Package (C/W) (C/W) 7050, 6-pin 142 27 5032, 6-pin 97 20 3225, 6-pin 109 20 Environmental Compliance Parameter Condition/Test Method Mechanical Shock MIL-STD-883F, Method 2002 Mechanical Vibration MIL-STD-883F, Method 2007 Temperature Cycle JESD22, Method A104 Solderability MIL-STD-883F, Method 2003 Moisture Sensitivity Level MSL1 260C Rev. 1.06 Page 2 of 8 www.sitime.com