DATA SHEET SKY12343-364LF: 0.01 4.0 GHz Seven-Bit Digital Attenuator with Serial and Parallel Drivers Applications Cellular and 3G infrastructure WiMAX, LTE, 4G infrastructure Features Broadband operation: 0.01 to 4.0 GHz Figure 1. SKY12343-364LF Block Diagram Attenuation range: 31.75 dB with 0.25 dB LSB TTL/CMOS-compatible serial, parallel, or latched parallel control interface Description Single supply voltage: +3.3 or +5 V The SKY12343-364LF is a GaAs broadband seven-bit pHEMT digital attenuator with a 0.25 dB Least Significant Bit (LSB). The Small, QFN (32-pin, 5 x 5 mm) Pb-free package (MSL1, 260 C programming logic levels are TTL/CMOS-compatible with both a per JEDEC J-STD-020) dual mode serial controller and an integrated Serial Peripheral Interface (SPI) controller. The SKY12343-364LF attenuator features low insertion loss, excellent attenuation accuracy, a 31.75 dB attenuation range, and high linearity performance. The device is an ideal choice for a wide variety of 3G and 4G cellular infrastructure applications. A functional block diagram is shown in Figure 1. The pin configuration and package are shown in Figure 2. Signal pin assignments and functional pin descriptions are provided in Table 1. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 201355C Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice March 7, 2012 1 DATA SHEET SKY12343-364LF SEVEN-BIT DIGITAL ATTENUATOR Figure 2. SKY12343-364LF Pinout 32-Pin QFN (Top View) Table 1. SKY12343-364LF Signal Descriptions Pin Name Description Pin Name Description 1 N/C No connection (Note 1) 17 N/C No connection (Note 1) 2 VDD DC power supply 18 RF2 RF input/output to digital attenuator 3 P/S Serial or parallel operation select. Logic low 19 N/C No connection (Note 1) enables parallel mode. 4 A0 Address bit A0 20 N/C No connection (Note 1) 5 N/C No connection (Note 1) 21 A2 Address bit A2 6 N/C No connection (Note 1) 22 A1 Address bit A1 7 RF1 RF input/output to digital attenuator 23 LATCH ENABLE On rising edge of pulse, shifts the most recent clocked-in data and address bits to set the attenuation state. In parallel mode, if this signal is logic high, changes to the V1 through V7 signals occur directly. If this signal is logic low, the attenuator does not change states until this signal is raised. 8 N/C No connection (Note 1) 24 CLOCK Clock input 9 N/C No connection (Note 1) 25 DATA IN Serial data input 10 N/C No connection (Note 1) 26 V1 Parallel attenuation control input 11 N/C No connection (Note 1) 27 V2 Parallel attenuation control input 12 N/C No connection (Note 1) 28 V3 Parallel attenuation control input 13 N/C No connection (Note 1) 29 V4 Parallel attenuation control input 14 N/C No connection (Note 1) 30 V5 Parallel attenuation control input 15 N/C No connection (Note 1) 31 V6 Parallel attenuation control input 16 N/C No connection (Note 1) 32 V7 Parallel attenuation control input Note 1: May be connected to ground with no change in performance. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 March 7, 2012 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice 201355C