DATA SHEET SKY65048-360LF: 0.7-1.2 GHz Low Noise Amplifier Applications Inter- x Wireless infrastructure: GSM, CDMA, WCDMA, ISM, and Stage TD-SCDMA Match x Ultra-low noise applications Figure 1. SKY65048-360LF Block Diagram Features x Ultra-low Noise Figure = 0.65 dB 900 MHz Description x Excellent input and output return loss The SKY65048-360LF is a high performance, two-stage ultra-low noise amplifier. The device is fabricated from Skyworks advanced x Adjustable gain = 16.5 to 21.5 dB 900 MHz pHEMT process and is provided in a 2 x 2 mm, 8-pin Quad Flat x High output OIP3 = +35.5 dBm 85 mA No-Lead (QFN) package. x OP1dB = +18.5 dBm 900 MHz The device features excellent input and output return loss, an x Single, positive DC supply voltage integrated interstage matching network, and integrated source x Adjustable supply current, 30 to 100 mA st nd inductors for 1 and 2 stage transistors. The amplifiers ultra- rd x Small, QFN (8-pin, 2 x 2 mm) package (MSL1, 260 q C per low Noise Figure (NF), high gain, and excellent 3 Order Intercept JEDEC J-STD-020) point (IP3) allow it to be used in various receiver and transmitter applications. A functional block diagram is shown in Figure 1. The pin configuration and package are shown in Figure 2. Signal pin assignments and functional pin descriptions are provided in Table 1. 8 1 BIAS1 BIAS2 2 7 RFIN RFOUT/VDD2 3 6 N/C N/C VDD1 4 5 FEEDBACK Figure 2. SKY65048-360LF Pinout 8-Pin QFN (Top View) Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 201101D Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 12, 2009 1 DATA SHEET SKY65048-360LF LOW NOISE AMPLIFIER Table 1. SKY65048-360LF Signal Descriptions Pin Name Description Pin Name Description st 1 BIAS1 Source lead for 1 stage transistor 5 FEEDBACK Connect to RFOUT/VDD2 to reduce gain of nd 2 stage transistor 2 RFIN RF input 6 N/C No connection 3 N/C No connection 7 RFOUT/VDD2 RF output. Requires a DC bias using an RF choke inductor. st nd 4 VDD1 1 stage DC power supply 8 BIAS2 Source lead for 2 stage transistor Source Inductance Functional Description The SKY65048-360LF is a two stage, low noise amplifier with an The source inductance required on pins 1 and 8 (BIAS1 and BIAS2 integrated interstage matching network and source inductors. The signals, respectively) has been integrated on the die. This device has a tested low NF of 0.65 dB and gain of 16.5 dB with simplifies board layout and reduces build variations. the recommended matching circuit. The device allows designers to adjust current and gain without degrading the NF. Input and Output RF Matching Network The external matching network largely dictates the RF The input band-pass matching network consists of four performance of the device. The matching network is required for components. Component C1 serves as the input DC blocking operation and special care should be taken when designing a capacitor, C2 provides high frequency stability and improved input circuit board layout for the SKY65048-360LF. There are four return loss, and L1 and L2 are responsible for the best noise separate groups of external components: input, output, biasing, match looking into the gate of the first stage amplifier. and feedback. Excess board trace should be eliminated at the input of the device to minimize board losses. High-Q components should be used to Biasing achieve the best NF of the amplifier. Murata GJM series To properly bias a depletion mode pHEMT, both the gate and capacitors and Coilcraft HP or CS series inductors are drain of the device must be biased properly. At VGS = 0 V and recommended. Any excess board or component loss on the input VDS > 2 V, the amplifier stage is in its saturated state and draws of the device directly adds to the total measured NF. the maximum amount of current, IDSS. A VDS of 5 V is The output matching network is band-pass network optimized for recommended to ensure proper performance. output return loss. To eliminate the need for a negative DC supply, self-biasing The SKY65048-360LF Evaluation Board assembly diagram is should be used when a resistor is placed between one of the shown in Figure 31 and a circuit schematic is provided in source leads and ground. A bypass capacitor should be placed in Figure 32. parallel to this resistor to provide an RF ground and to ensure performance remains unchanged at the operating frequency. Feedback When current flows from drain to source and through the resistor, nd Feedback is implemented in the recommended circuit on the 2 the source voltage becomes biased above DC ground. The gate stage transistor. Feedback improves the input and output return pin of the device should be left unbiased at 0 V, which creates the loss and high frequency stability. The gain of the device can be desired negative VGS value. This simplifies the design by increased by increasing the value of R3, which reduces the eliminating the need for a second DC supply. Values for resistor amount of feedback present (gain for multiple feedback resistor components R1 and R2 can be changed to easily increase or values is shown in Figure 30). decrease the bias current to a desired level. The first stage is biased at 20 percent of IDSS to achieve the best nd NF performance. The gain and current of the 2 stage amplifier can be adjusted without degrading the overall NF. More current in nd the 2 stage yields better IP3 performance. Biasing components R1, R2, C1, and C2 should be placed as close to the package pins as possible. See Figure 30 for the recommended board layout. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 November 12, 2009 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice 201101D