DATA SHEET SKY65084-360LF: 1.5-2.4 GHz Low Noise Amplifier Applications Inter- x Wireless infrastructure: GSM, CDMA, WCDMA, and TD-SCDMA Stage Match x Ultra low-noise applications Features Figure 1. SKY65084-360LF Block Diagram x Ultra-low Noise Figure = 0.70 dB 1.95 GHz Description x Excellent input and output return loss The SKY65084-360LF is a high performance, two-stage ultra low- x Adjustable gain = 15 to 25 dB 1.95 GHz noise amplifier. The device is fabricated from Skyworks advanced x High output OIP3 = +34.0 dBm 65 mA pHEMT process and is provided in a 2 x 2 mm, 8-pin Quad Flat x OP1dB = +16 dBm 1.95 GHz No-Lead (QFN) package. x Single, positive DC supply voltage The device features excellent input and output return loss, and an x Adjustable supply current, 30 to 100 mA integrated interstage matching network. The amplifiers ultra-low rd Noise Figure (NF), high gain, and excellent 3 Order Intercept x Small, QFN (8-pin, 2 x 2 mm) package (MSL1, 260 q C per point (IP3) allow it to be used in various receiver and transmitter JEDEC J-STD-020) applications. A functional block diagram is shown in Figure 1. The pin configuration and package are shown in Figure 2. Signal pin assignments and functional pin descriptions are provided in Table 1. 8 1 N/C VDD1 7 2 RFOUT/VDD2 RFIN 6 3 N/C BIAS1 FEEDBACK 5 4 BIAS2 Figure 2. SKY65084-360LF Pinout 8-Pin QFN (Bottom View) Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 201107C Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 12, 2009 1 DATA SHEET SKY65084-360LF LOW NOISE AMPLIFIER Table 1. SKY65084-360LF Signal Descriptions Pin Name Description Pin Name Description st nd 1 VDD1 1 stage DC power supply 5 FEEDBACK Connect to RFOUT to reduce gain of 2 stage transistor 2 RFIN RF input 6 N/C No connection st 3 BIAS1 Source lead for 1 stage transistor 7 RFOUT/VDD2 RF output. Requires a DC bias using an RF choke inductor. nd 4 BIAS2 Source lead for 2 stage transistor 8 N/C No connection 1 8 Inter-Stage Match 2 7 3 6 4 5 S1500 Figure 3. SKY65084-360LF On-Die Functional Diagram source leads and ground. A bypass capacitor should be placed in Functional Description parallel to this resistor to provide an RF ground and to ensure The SKY65084-360LF is a two stage, low noise amplifier with an performance remains unchanged at the operating frequency. integrated interstage matching network. The device has a tested low NF of 0.70 dB and gain of 24 dB. The device allows designers When current flows from drain to source and through the resistor, to adjust current and gain without degrading the NF. the source voltage becomes biased above DC ground. The gate pin of the device should be left unbiased at 0 V, which creates the The external matching network largely dictates the RF desired negative VGS value. This simplifies the design by performance of the device. The matching network is required for eliminating the need for a second DC supply. Values for resistor operation and special care should be taken when designing a components R1 and R2 can be changed to easily increase or circuit board layout for the SKY65084-360LF. There are four decrease the bias current to a desired level. separate groups of external components: input, output, biasing, and feedback. Figure 3 illustrates the circuit-on-die inside the The first stage is biased at 20 percent of IDSS to achieve the best nd 2 x 2 mm QFN package. NF performance. The gain and current of the 2 stage amplifier can be adjusted without degrading the overall NF. More current in nd the 2 stage yields better IP3 performance. Biasing Components L3 and L4 are the RF bias choke inductors (refer to To properly bias a depletion mode pHEMT, both the gate and Figure 18). These are required to block RF power and pass VDD to drain of the device must be biased properly. At VGS = 0 V and the drain of each amplifier stage. Components C5, C6, C7, C9, VDS > 2 V, the amplifier stage is in its saturated state and draws and C10 are RF bypass capacitors. R3 and R4 reduce the voltage the maximum amount of current, IDSS. A VDS of 5 V is presented at the drain of each stage of the device. The resistor recommended to ensure proper performance. rd values are optimized for 3 Order Output Intercept Point (OIP3) To eliminate the need for a negative DC supply, self-biasing and P1dB performance. should be used when a resistor is placed between one of the Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 November 12, 2009 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice 201107C