EVALSTGAP2HSM STMicroelectronics

EVALSTGAP2HSM Data brief Demonstration board for STGAP2HSM isolated 4 A single gate driver Features Board High voltage rail up to 1200 V Negative gate driving Onboard isolated DC-DC converters to supply high-side and low-side gate drivers, fed by VAUX = 5 V, with 5.2 kV maximum isolation 3.3 V VDD logic supply generated onboard or 5 V (externally applied) Easy jumper selection of driving voltage configuration: +15/0 V +15/-3 V +19/0 V +19/-3 V Device Driver current capability: 4 A source/sink 25C Separate sink and source for easy gate driving configuration 6000 V Galvanic isolation Short propagation delay: 75 ns UVLO function Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shutdown protection Standby function Description Product status link The EVALSTGAP2HSM is an isolated single gate driver. EVALSTGAP2HSM The gate driver is characterized by 4 A current capability and rail-to-rail outputs, making the device suitable also for high power inverter applications such as motor drivers in industrial applications equipped with MOSFET / IGBT power switch. The separated source and sink outputs allow to independently optimize turn-on and turn-off by using dedicated gate resistors. The device integrates protection functions: UVLO and thermal shutdown are included to easily design high reliability systems. Dual input pins allow choosing the control signal polarity and also implementing HW interlocking protection in order to avoid cross-conduction in case of controller s malfunction. The device allows implementing negative gate driving, and the onboard isolated DC- DC converters allow working with optimized driving voltage for MOSFET/IGBT. The EVALSTGAP2HSM board allows evaluating all the STGAP2HSM features while driving a half-bridge power stage with voltage rating up to 1200 V in TO-220 or TO-247 package. The board allows easily selecting and modifying the values of relevant external components in order to ease driver performance evaluation under different applicative conditions and fine pre-tuning of the final applications components. DB4269 - Rev 1 - September 2020 www.st.com For further information contact your local STMicroelectronics sales office.EVALSTGAP2HSM Schematic diagram 1 Schematic diagram Figure 1. EVALSTGAP2HSM circuit schematic gate drivers J1 1 C IN+H IN+ H TP1 2 C IN-H IN- H TP2 3 C IN+L IN+ L TP3 4 C IN-L IN- L TP4 5 GND TP5 6 VDD VDD TP6 7 VAUX VAUX TP7 CN1 TE 928814-1 1 HV 1 2 J2 VDD R1 22R 2 GH C IN+H 1 IN+ H HV 2 C IN-H IN- H HV C IN+L 3 IN+ L C1 D1 4 C IN-L IN- L 2 100nF/50V STPS2L40ZFY TP8 VDD VH H 2 5 C2 GND U1 STGAP2HSM 6 VDD 100nF/50V Q2 VDD R2 2R2 7 VAUX 1 5 1 N.M. VAUX VAUX VH H VDD VH GH 1 TO247 R3 100R JP1 C IN+H IN+H 2 6 GONUH Q2A IN+ GON CLOSED C4 C3 N.M. R4 100R CN2 TE 928814-1 3 TP9 C IN-H IN-H 3 7 GOFCH JP3 TO220 3 IN- GOFF N.M. CLOSED 1uF 50V 1 GND JP2 OPEN OUT OUT 1 4 8 GNDISO H 2 GND GNDISO 2 C5 C6 GNDISO H 220pF/25V 220pF/25V TP10 OUT GNDISO H TP11 C7 1uF 50V JP4 CLOSED C IN-L C IN+H VH L VH H JP5 CLOSED D2 C IN+L C IN-H R5 2 1 JP6 OPEN N.M. STTH112A C IN-L C IN-H VDD 10-20R R6 22R GL OUT C8 D3 100nF/50V STPS2L40ZFY 2 2 VDD VH L C9 U2 STGAP2HSM 100nF/50V Q1 R8 2R2 1 5 VH L 1 N.M. GL 1 VDD VH TO247 R7 100R JP7 Q1A C IN+L IN+L 2 6 GONUL IN+ GON CLOSED C10 C11 N.M. R9 100R CN3 TE 928814-1 TO220 3 3 C IN-L IN-L 3 7 GOFCL JP9 IN- GOFF 1uF 50V N.M. CLOSED 1 JP8 OPEN 1 4 8 GNDISO L GNDPWR 2 GND GNDISO 2 C12 C13 GNDISO L TP12 220pF/25V 220pF/25V GNDPWR GNDISO L C14 1uF 50V TP13 EVALSTGAP2HS Version: R1.0 VP1 FULL 2HSM VP2 EMPTY 2HSCM VP3 EMPTY VP4 EMPTY DB4269 - Rev 1 page 2/12 2 1 2 1