EVALSTGAP2SICD STMicroelectronics

EVALSTGAP2SICD Data brief Demonstration board for EVALSTGAP2SICD isolated 4 A half-bridge gate driver Features Board High voltage rail up to 1200 V Negative gate driving On-board isolated DC-DC converters to supply high-side and low-side gate drivers, fed by VAUX = 5 V, with 5.2 kV maximum isolation VDD logic supplied by on-board generated 3.3 V or VAUX = 5V Easy jumper selection of driving voltage configuration: +17/0 V +17/-3 V +19/0 V +19/-3 V Device Driver current capability: 4 A source/sink 25C 4 A Miller CLAMP Short propagation delay: 75 ns UVLO function Configurable interlocking function Dedicated SD and BRAKE pins Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shutdown protection Standby function Product status link Description EVALSTGAP2SICD The EVALSTGAP2SICD is an half bridge evaluation board designed to evaluate the STGAP2SiCD isolated dual gate driver. The gate driver is characterized by 4 A current capability and rail-to-rail outputs, making the device suitable also for high power applications such as motor drivers in industrial applications equipped with SiC power switches. The device integrates protection functions: dedicated SD and BRAKE pins are available, UVLO and thermal shutdown are included to easily design high reliability systems, and the interlocking function prevents outputs from being high at the same time. The device allows implementing negative gate driving, and the on-board isolated DC-DC converters allows working with optimized driving voltage for SiC MOSFETs. The EVALSTGAP2SICD board allows evaluating all the STGAP2SICD features while driving a half-bridge power stage with voltage rating up to 1200 V in TO-220 or TO-247 package. The board allows easily selecting and modifying the values of relevant external components in order to ease driver performance evaluation under different applicative conditions and fine pre-tuning of final application components. DB4544 - Rev 1 - October 2021 www.st.com For further information contact your local STMicroelectronics sales office.EVALSTGAP2SICD Schematic diagram 1 Schematic diagram Figure 1. EVALSTGAP2SICD schematic gate driver DB4544 - Rev 1 page 2/12 J1 VDD VDD 1 GND 2 PWMA INA 3 PWMB INB 4 SD IN SD 5 BRAKE IN BRAKE 6 VAUX 7 VAUX J2 VDD 1 VDD 2 GND 3 PWMA INA 4 PWMB D1 R1 VH B INB 5 SD IN 1 2 SD 6 BRAKE IN BRAKE 7 VAUX VAUX STTH112A N.M. CN1 HV HV 20-30R 1 1 VH A 2 2 TP2 TE 928814-1 TP1 2 TP3 VH A U1 STGAP2SiCD Q1/A R2 22R GON A VDD TP4 30 GH 1 VH A C1 VH A 100nF/50V N.M. 6 31 3 VDD GON A TP5 R3 2.2R C2 C3 GOFF A 32 VDD GOFF A CN2 OUT C4 C5 INA 7 1uF/50V N.M. TP7 INA INB 8 35 TP6 JP3 1 4.7uF/16V 100nF/16V TP8 INB GNDISO A 1 GNDISO A SD 9 34 OUT 2 TP9 SD GNDISO A 2 R20 BRAKE 10 33 GH TP11 VH B CLOSED BRAKE CLAMP A 0 TP10 GNDISO A VH B TE 928814-1 20 TP13 VH B 11 TP12 C6 1uF/50V iLOCK GON B 22 2 GON B TP15 23 Q2/A R5 GND GOFF B R4 22R 13 1 N.M. GL GND 24 VH B GNDISO B N.M. TP14 3 C9 25 GL C8 R6 2.2R C10 CLAMP B GOFF B 100nF/50V TP17 CN3 GNDPWR 1uF/50V N.M. TP16 JP6 1 GNDISO B 1 2 2 CLOSED GNDISO B TE 928814-1 R7 R8 PWMA INA PWMB INB C11 1uF/50V 100R C12 100R C13 220pF/25V 220pF/25V VDD VDD R9 R10 R11 10K R12 10K BRAKE IN SD IN BRAKE SD 100R C14 100R C15 1nF/25V 1nF/25V