HCF4015B DUAL 4-STAGE STATIC SHIFT REGISTER WITH SERIAL INPUT/PARALLEL OUTPUT MEDIUM SPEED OPERATION 12 MHz (Typ.) CLOCK RATE AT V - V = 10V DD SS FULLY STATIC OPERATION 8 MASTER-SLAVE FLIP-FLOPS PLUS INPUT AND OUTPUT BUFFERING HIGH NOISE IMMUNITY DIP SOP QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT ORDER CODES I = 100nA (MAX) AT V = 18V T = 25C I DD A PACKAGE TUBE T & R 100% TESTED FOR QUIESCENT CURRENT DIP HCF4015BEY MEETS ALL REQUIREMENTS OF JEDEC SOP HCF4015BM1 HCF4015M013TR JESD13BSTANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICE four stages on both registers. All register stages DESCRIPTION are D-TYPE, MASTER-SLAVE flip-flops. The logic level present at the DATA input is transferred HCF4015B is a monolithic integrated circuit into the first register stage and shifted over one fabricated in Metal Oxide Semiconductor stage at each positive going clock transition. The technology available in DIP and SOP packages. resetting of all stages is accomplished by a high HCF4015B consists of two identical, independent, level on the reset line. It is possible to expand the 4 stage serial-input/parallel-output registers. register to 8 stages using one HCF4015B Each register has independent CLOCK and package and to expand to more than 8 stages by RESET inputs as well as a single serial DATA using addition HCF4015Bs. input. outputs are available from each of the PIN CONNECTION September 2002 1/10HCF4015B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION CLOCK A 1, 9 Clock Input CLOCK B RESET A 6, 14 Reset Input RESET B DATA A 7, 15 Data Inputs DATA B 5, 4, 3, 10 QnA Outputs A-Stage 13, 12, 11, 2 QnB Outpus B-Stage 8 V Negative Supply Voltage SS V 16 Positive Supply Voltage DD FUNCTIONAL DIAGRAM TRUTH TABLE CLOCK D R Q Q 1 n LLL Q - 1 n Q - 1 HL H n Q Q - (NO CHANGE) XL 1 n XX H L 0 X : Dont Care 2/10