N74F166N NXP

INTEGRATED CIRCUITS 74F166 8-bit bidirectional universal shift register Product specification 1991 Feb 14 IC15 Data Handbook Philips Semiconductors Product specification 8-bit bidirectional universal shift register 74F166 FEATURES For expansion of the register in parallel to serial converters, the Q7 output is connected to the Ds input of the succeeding High impedance NPN base inputs for reduced loading stage. The clock input is gated OR structure which allows (20A in high and low states) Synchronous parallel to serial applications one input to be used as an activelow clock enable (CE) Synchronous serial data input for easy expansion input. The pin assignment for the CP and CE inputs is Clock enable for do nothing mode arbitrary and can be reversed for layout convenience. The Asynchronous master reset lowtohigh transition of CE input should only take place Expandable to 16 bits in 8bit increments while the CP is high for predictable operation. A low on the Industrial temperature range available (40C to +85C) master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a low DESCRIPTION state. The 74F166 is a high speed 8bit shift register that has fully synchronous serial parallel data entry selected by an active low parallel enable (PE) input. When the PE is low one setup TYPE TYPICAL f TYPICAL SUPPLY CUR- max time before the lowtohigh clock transition, parallel data is RENT( TOTAL) entered into the register. 74F166 175MHz 50mA When PE is high, data is entered into internal bit position Q0 from serial data input (Ds), and the remaining bits are shifted one place to the right (Q0 Q1 Q2, etc.) with each positive going clock transition. ORDERING INFORMATION ORDER CODE COMMERCIAL RANGE INDUSTRIAL RANGE DESCRIPTION PKG DWG V = 5V 10%, V = 5V 10%, CC CC T = 0C to +70C T = 40C to +85C amb amb 16pin plastic DIP N74F166N I74F166N SOT38-4 16pin plastic SO N74F166D I74F166D SOT109-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/ LOAD VALUE HIGH/ LOW LOW 20A/20A D0 D7 Parallel data inputs 1.0/0.033 Ds Serial data input (shift right) 2.0/0.066 40A/40A CP Clock input (active rising edge) 1.0/0.033 20A/20A CE Clock enable input (active low) 1.0/0.033 20A/20A 20A/20A PE Parallel enable input (active low) 1.0/0.033 40A/40A MR Master reset input (active low) 2.0/0.066 1.0mA/20mA Q7 Data output 50/33 Note to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state. 2 Feb. 14, 1991 8530349 01718