LNBH25SPQR STMicroelectronics

LNBH25S LNB supply and control IC with step-up and IC interface Datasheet - production data Low drop post regulator and high efficiency step-up PWM with integrated power NMOS allowing low power losses LPM function (low power mode) to reduce dissipation Overload and overtemperature internal protections with IC diagnostic bits LNB short-circuit dynamic protection +/- 4 kV ESD tolerant on output power pins Applications STB satellite receivers Features TV satellite receivers Complete interface between LNB and IC PC card satellite receivers bus Built-in DC-DC converter for single 12 V Description supply operation and high efficiency Intended for analog and digital satellite (typ. 93% 0.5 A) receivers/Sat-TV and Sat-PC cards, the Selectable output current limit by external LNBH25S is a monolithic voltage regulator and resistor interface IC, assembled in QFN24L (4x4 mm) Compliant with main satellite receiver output specifically designed to provide 13/18 V power voltage specifications (15 programmable supply and 22 kHz tone signaling to the LNB levels) down-converter in the antenna dish or to the Accurate built-in 22 kHz tone generator suits multi-switch box. In this application field, it offers widely accepted standards a complete solution with extremely low 22 kHz tone waveform integrity guaranteed component count and low power dissipation at no-load condition together with a simple design and IC standard interface. Table 1: Device summary Order code Package Packing LNBH25SPQR QFN24L (4x4) Tape and reel October 2016 DocID026736 Rev 3 1/37 www.st.com This is information on a product in full production. Contents LNBH25S Contents 1 Block diagram .................................................................................. 6 2 Application information .................................................................. 7 2.1 DiSEqC data encoding (DSQIN pin) ................................................. 7 2.2 Data encoding by external 22 kHz tone TTL signal ........................... 7 2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin ...................................................................................................... 8 2.4 LPM (low power mode) ..................................................................... 8 2.5 DiSEqC 2.0 implementation .............................................................. 8 2.6 Output current limit selection ............................................................. 9 2.7 Output voltage selection .................................................................... 9 2.8 Diagnostic and protection functions .................................................. 9 2.9 Surge protections and TVS diodes .................................................... 9 2.10 FLT (fault flag) ................................................................................. 10 2.11 VMON (output voltage diagnostic) .................................................. 10 2.12 TMON (22 kHz tone diagnostic) ...................................................... 10 2.13 TDET (22 kHz tone detection) ......................................................... 10 2.14 IMON (minimum output current diagnostic) ..................................... 10 2.15 PDO (overcurrent detection on output pull-down stage) ................. 11 2.16 Power-on IC interface reset and undervoltage lockout .................. 11 2.17 PNG (input voltage minimum detection) .......................................... 11 2.18 ISW (inductor switching current limit) .............................................. 11 2.19 COMP (boost capacitors and inductor) ........................................... 11 2.20 OLF (overcurrent and short-circuit protection and diagnostic) ........ 12 2.21 OTF (thermal protection and diagnostic) ......................................... 12 3 Pin configuration ........................................................................... 13 4 Maximum ratings ........................................................................... 15 5 Typical application circuits ........................................................... 16 6 IC bus interface ............................................................................ 19 6.1 Data validity..................................................................................... 19 6.2 Start and stop condition .................................................................. 19 6.3 Byte format ...................................................................................... 19 6.4 Acknowledge ................................................................................... 19 2/37 DocID026736 Rev 3