M74HC299 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR HIGH SPEED : f = 80MHz (TYP.) at V = 6V MAX CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 6mA (MIN) FOR QA TO QH OH OL I = I = 4mA (MIN) FOR QA TO QH OH OL BALANCED PROPAGATION DELAYS: ORDER CODES t t PLH PHL PACKAGE TUBE T & R WIDE OPERATING VOLTAGE RANGE: DIP M74HC299B1R V (OPR) = 2V to 6V CC SOP M74HC299M1R M74HC299RM13TR PIN AND FUNCTION COMPATIBLE WITH TSSOP M74HC299TTR 74 SERIES 299 DESCRIPTION high, the eight input/output terminals are in the The M74HC299 is an high speed CMOS 8 BIT high impedance state however sequential PIPO SHIFT REGISTER (3-STATE) fabricated operation or clearing of the register is not affected. 2 with silicon gate C MOS technology. Clear function on the M74HC299 is asynchronous This device has four modes (HOLD, SHIFT LEFT, to CLOCK. SHIFT RIGHT and LOAD DATA). Each mode is All inputs are equipped with protection circuits chosen by two function select inputs (S0, S1). against static discharge and transient excess When one or both enable inputs, (G1, G2) are voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/13M74HC299 IINPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 19 S0, S1 Mode Select Inputs 2, 3 G1, G2 3-State Output Enable Inputs (Active LOW) 7, 13, 6, 14, 5, 15, 4, 16 A/QA to H/QH Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver) 8, 17 QA to QH Serial Outputs (Standard Output) 9 CLEAR Asynchronous Master Reset Input (Active LOW) 11 SR Serial Data Shift Right Input 12 CLOCK Clock Input (LOW to HIGH, Edge-triggered) 18 SL Serial Data Shift Left Input 10 GND Ground (0V) 20 V Positive Supply Voltage CC TRUTH TABLE INPUTS INPUTS/OUTPUTS OUTPUTS FUNCTION OUTPUT MODE SERIAL SELECTED CONTROL CLEAR CLOCK A/QA H/QH QA QH S1 S0 G1*G2*SLSR Z L H H X XXX X Z Z L L L L X L L X X X LLLL CLEAR L X L L L X X X LLLL HOLD H L L L L X X X QA0 QH0 QA0 QH0 H L H L L X H H QGn H QGn SHIFT RIGHT H L H L L X L L QGn L QGn H H L L L H X QBnH QBnH SHIFT LEFT H H L L L L X QBnL QBnL LOAD H H H X X X X ahah * When one or both output controls are high, the eight input/output terminals are in the high impedance state: however sequential operation or clearing of the register is not affected. Z : High Impedance Qn0 : The level of An before the indicated steady state input conditions were established. Qnn : The level of Qn before the most recent active transition indicated by OR a, h : The level of the steady state inputs A, H, respectively. X : Dont Care 2/13