MC10EP142, MC100EP142 3.3 V / 5 VECL 9-Bit Shift Register The MC10EP/100EP142 is a 9bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in www.onsemi.com only one direction. The nine inputs D0 D8 accept parallel input data, while SIN accepts serial input data. The QT0:87 outputs do not need MARKING to be terminated for the shift operation to function. To minimize DIAGRAM* power, any Q output not used should be left unterminated. The SEL (Select) input pin is used to switch between the two modes of operation SHIFT and LOAD. The shift direction is from Bit 0 to MCxxx Bit 8. Input data is accepted by the registers a setup time before the EP142 positive going edge of CLK0 or CLK1 shifting is also accomplished LQFP32 AWLYYWWG on the positive clock edge. A HIGH on the Master Reset pin (MR) FA SUFFIX asynchronously resets all the registers to zero, overriding CLK0 and CASE 873A CLK1 inputs. The 100 Series contains temperature compensation. 1 Features MCxxx Shift Frequency >2.8 GHz (Typical) 1 32 EP142 9-Bit for ByteParity Applications QFN32 AWLYYWW Asynchronous Master Reset MN SUFFIX CASE 488AM Dual Clocks PECL Mode Operating Range: V = 3.0 V to 5.5 V CC xxx = 10 or 100 with V = 0 V EE A = Assembly Location WL = Wafer Lot NECL Mode Operating Range: V = 0 V CC YY = Year with V = 3.0 V to 5.5 V EE WW = Work Week Open Input Default State G or = PbFree Package (Note: Microdot may be in either location) Safety Clamp on Inputs *For additional marking information, refer to These Devices are PbFree and are RoHS Compliant Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: April, 2015 Rev. 18 MC10EP142/DMC10EP142, MC100EP142 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17 25 16 D6 V EE D6 25 16 V EE 15 26 D5 Q4 26 15 D5 Q4 D4 27 14 Q3 27 14 D4 Q3 28 13 28 13 V V V EE EE CC V MC10EP142 CC Exposed Pad (EP) MC100EP142 29 12 12 D3 Q2 D3 29 Q2 30 11 D2 Q1 30 11 Q1 D2 31 10 D1 Q0 31 10 D1 Q0 32 9 V CC MR 32 9 V MR 123 456 78 CC 1 2345 6 7 8 Figure 1. Pinout: LQFP32 (Top View) Figure 2. Pinout: QFN32 (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Default State Description 1,31,30,29,27, D 0:8 ECL Input Low SingleEnded Parallel Data Inputs 0:8 . Internal 75 k to V . EE 26,25,24,23 2 SIN ECL Input Low Noninverted Differential Serial Input. Internal 75 k to V . EE 3 SIN ECL Input High Inverted Differential Serial Input. Internal 75 k to V and 36.5 k to EE V . CC 4 CLK0 ECL Input Low Noninverted Differential CLK0 Input. Internal 75 k to V . EE 5 CLK0 ECL Input High Inverted Differential CLK0B Input. Internal 75 k to V and 36.5 k EE to V . CC 6 CLK1 ECL Input Low Noninverted Differential CLK1 Input. Internal 75 k to V . EE 7 CLK1 ECL Input High Inverted Differential CLK1B Input. Internal 75 k to V and 36.5 k EE to V . CC 8 SEL ECL Input Low SingleEnded Select Logic Input. Internal 75 k to V . EE 9 MR ECL Input Low SingleEnded Master Reset Logic Input. Internal 75 k to V . EE 10,11,12,14,1 Q0,Q1,Q2,Q3, ECL Output SingleEnded parallel Data outputs 0,1,2,3,4,5,6,8 . Typically 5,18,19,22 Q4,Q5,Q6,Q8 Terminated with 50 to V = V 2 V. TT CC 13,17,32 V Positive supply Voltage. All V Pins must be Externally Connected to CC CC Power Supply to Guarantee Proper Operation. 16,28 V Negative supply Voltage. All V Pins must be Externally connected EE EE to Power Supply to Guarantee Proper Operation. 20 Q7 ECL Output Noninverted Differential parallel/Serial Data Output 7. Typically Terminated with 50 to V = V 2 V. TT CC 21 Q7 ECL Output Inverted Differential parallel/Serial Data Output 7. Typically Terminated with 50 to V = V 2 V. TT CC 1. All V and V pins must be externally connected to Power Supply to guarantee proper operation. CC EE www.onsemi.com 2 D0 D7 D8 SIN Q8 SIN CLK0 Q7 CLK0 Q7 CLK1 Q6 CLK1 Q5 SEL V CC D0 D7 SIN D8 SIN Q8 CLK0 Q7 Q7 CLK0 CLK1 Q6 Q5 CLK1 SEL V CC