MC10EP142, MC100EP142 3.3 V / 5 V ECL 9Bit Shift Register The MC10EP/100EP142 is a 9bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in MC10EP142, MC100EP142 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17 25 16 D6 V EE D6 25 16 V EE 15 26 D5 Q4 26 15 D5 Q4 27 D4 14 Q3 27 14 D4 Q3 28 13 28 13 V V V EE EE CC MC10EP142 V CC Exposed Pad (EP) MC100EP142 29 12 29 12 D3 Q2 D3 Q2 30 11 D2 Q1 30 11 Q1 D2 31 10 D1 Q0 31 10 D1 Q0 32 9 V CC MR 32 9 V MR 1234567 8 CC 1 234 5 6 78 Figure 1. Pinout: LQFP32 (Top View) Figure 2. Pinout: QFN32 (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Default State Description 1,23,24,25,26, D 0:8 ECL Input Low Single Ended Parallel Data Inputs 0:8 . Internal 75 k to V . EE 27,29,30,31 2 SIN ECL Input Low Noninverted Differential Serial Input. Internal 75 k to V . EE 3 SIN ECL Input High Inverted Differential Serial Input. Internal 75 k to V and 36.5 k to EE V . CC 4 CLK0 ECL Input Low Noninverted Differential CLK0 Input. Internal 75 k to V . EE 5 CLK0 ECL Input High Inverted Differential CLK0B Input. Internal 75 k to V and 36.5 k EE to V . CC 6 CLK1 ECL Input Low Noninverted Differential CLK1 Input. Internal 75 k to V . EE 7 CLK1 ECL Input High Inverted Differential CLK1B Input. Internal 75 k to V and 36.5 k EE to V . CC 8 SEL ECL Input Low Single Ended Select Logic Input. Internal 75 k to V . EE 9 MR ECL Input Low Single Ended Master Reset Logic Input. Internal 75 k to V . EE 10,11,12,14,1 Q0,Q1,Q2,Q3, ECL Output Single Ended parallel Data outputs 0,1,2,3,4,5,6,8 . Typically 5,18,19,22 Q4,Q5,Q6,Q8 Terminated with 50 to V = V 2 V. TT CC 13,17,32 V Positive supply Voltage. All V Pins must be Externally Connected to CC CC Power Supply to Guarantee Proper Operation. 16,28 V Negative supply Voltage. All V Pins must be Externally connected EE EE to Power Supply to Guarantee Proper Operation. 20 Q7 ECL Output Noninverted Differential parallel/Serial Data Output 7. Typically Terminated with 50 to V = V 2 V. TT CC 21 Q7 ECL Output Inverted Differential parallel/Serial Data Output 7. Typically Terminated with 50 to V = V 2 V. TT CC 1. All V and V pins must be externally connected to Power Supply to guarantee proper operation. CC EE