ST6208C ST6209C ST6210C ST6220C 8-bit MCUs with A/D converter, two timers, oscillator safeguard & safe reset Memories 1K, 2K or 4K bytes Program memory (OTP, EPROM, FASTROM or ROM) with read-out protection 64 bytes RAM Clock, Reset and Supply Management PDIP20 Enhanced reset system Low Voltage Detector (LVD) for Safe Reset Clock sources: crystal/ceramic resonator or RC network, external clock, backup oscillator (LFAO) SO20 Oscillator Safeguard (OSG) 2 Power Saving Modes: Wait and Stop Interrupt Management 4 interrupt vectors plus NMI and RESET SSOP20 12 external interrupt lines (on 2 vectors) 12 I/O Ports 12 multifunctional bidirectional I/O lines 8 alternate function lines 4 high sink outputs (20mA) CDIP20W 2 Timers Configurable watchdog timer (See Section 11.5 for Ordering Information) 8-bit timer/counter with a 7-bit prescaler Instruction Set Analog Peripheral 8-bit data manipulation 8-bit ADC with 4 or 8 input channels (except 40 basic instructions on ST6208C) 9 addressing modes Bit manipulation Development Tools Full hardware/software development package Device Summary Features ST6208C ST6209C ST6210C ST6220C Program memory 1K 2K 4K - bytes RAM - bytes 64 Operating Supply 3.0V to 6V Analog Inputs - 48 Clock Frequency 8MHz Max Operating -40C to +125C Temperature Packages PDIP20/SO20/SSOP20 January 2009 Rev 4 1/104 1 Obsolete Product(s) - Obsolete Product(s)Table of Contents 1 INTRODUCTION 6 2 PIN DESCRIPTION 7 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES 9 3.1 MEMORY AND REGISTER MAPS 9 3.1.1 Introduction 9 3.1.2 Program Space 11 3.1.3 Readout Protection . 11 3.1.4 Data Space . 11 3.1.5 Stack Space . 11 3.1.6 Data ROM Window . 13 3.2 PROGRAMMING MODES 15 3.2.1 Program Memory . 15 3.2.2 EPROM Erasing 15 3.3 OPTION BYTES . 16 4 CENTRAL PROCESSING UNIT . 17 4.1 INTRODUCTION . 17 4.2 MAIN FEATURES 17 4.3 CPU REGISTERS 17 5 CLOCKS, SUPPLY AND RESET 19 5.1 CLOCK SYSTEM . 19 5.1.1 Main Oscillator . 20 5.1.2 Oscillator Safeguard (OSG) . 21 5.1.3 Low Frequency Auxiliary Oscillator (LFAO) . 22 5.1.4 Register Description . 22 5.2 LOW VOLTAGE DETECTOR (LVD) 23 5.3 RESET . 24 5.3.1 Introduction . 24 5.3.2 RESET Sequence 24 5.3.3 RESET Pin 25 5.3.4 Watchdog Reset . 26 5.3.5 LVD Reset 26 5.4 INTERRUPTS . 27 5.5 INTERRUPT RULES AND PRIORITY MANAGEMENT . 28 5.6 INTERRUPTS AND LOW POWER MODES 28 5.7 NON MASKABLE INTERRUPT 28 5.8 PERIPHERAL INTERRUPTS . 28 5.9 EXTERNAL INTERRUPTS (I/O PORTS) 29 5.9.1 Notes on using External Interrupts 29 5.10 INTERRUPT HANDLING PROCEDURE . 30 5.10.1Interrupt Response Time . 30 5.11 REGISTER DESCRIPTION . 31 104 6 POWER SAVING MODES . 32 6.1 INTRODUCTION . 32 2/104 2 Obsolete Product(s) - Obsolete Product(s)