ST72325xx 8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 2 5 timers, SPI, SCI, I C interface Features Memories 16K to 60K dual voltage High Density Flash (HDFlash) or up to 32K ROM with read-out LQFP64 LQFP44 LQFP48 LQFP32 protection capability. In-Application Program- 10 x 10 10 x 10 7 x 7 7 x 7 ming and In-Circuit Programming for HDFlash devices 512 to 2048 bytes RAM HDFlash endurance: 100 cycles, data reten- tion: 40 years at 85C LQFP64 SDIP42 SDIP32 Clock, reset and supply management 14 x 14 600 mil 400 mil Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector Configurable watchdog timer (AVD) with interrupt capability Two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- Clock sources: crystal/ceramic resonator os- er, PWM and pulse generator modes cillators, internal RC oscillator and bypass for external clock 8-bit PWM Auto-reload timer with: 2 input cap- PLL for 2x frequency multiplication tures, 4 PWM outputs, output compare and time base interrupt, external clock with event Four Power Saving Modes: Halt, Active-Halt, detector Wait and Slow 3 Communication interfaces Clock Security System SPI synchronous serial interface Interrupt management SCI asynchronous serial interface Nested interrupt controller 2 I C multimaster interface 14 interrupt vectors plus TRAP and RESET 1 Analog peripheral (low current coupling) Top Level Interrupt (TLI) pin on 64-pin devices 10-bit ADC with up to 16 robust input ports 9/6 external interrupt lines (on 4 vectors) Instruction set Up to 48 I/O ports 8-bit Data Manipulation 48/36/32/24 multifunctional bidirectional I/O lines 63 Basic Instructions 34/26/22/17 alternate function lines 17 main Addressing Modes 16/13/12/10 high sink outputs 8 x 8 Unsigned Multiply Instruction 5 timers Development tools Main Clock Controller with: Real time base, Full hardware/software development package Beep and Clock-out capabilities DM (Debug module) Table 1. Device summary ST72325R9 / ST72325S4 / ST72325S6 / Features ST72325J7 ST72325AR9 / ST72325J4 / ST72325K4 ST72325J6 / ST72325K6 ST72325C9 /ST72325J9 Program memory - bytes Flash/ROM 16K Flash/ROM 32K Flash 48K Flash 60K RAM (stack) - bytes 512 (256) 1024(256) 1536 (256) 2048(256) Operating Voltage 3.8V to 5.5V Temp. Range up to -40C to +125C LQFP64 14x14(R), LQFP64 LQFP48(S), LQFP44/SDIP42 (J), LQFP48(S) , LQFP44/ SDIP42 (J), Package LQFP44 (J) 10x10(AR), LQFP48(C), LQFP32/DIP32 (K) LQFP32/DIP32 (K) LQFP44 (J) October 2008 Rev 4 1/197 1Table of Contents 1 DESCRIPTION . 7 2 PIN DESCRIPTION 8 3 REGISTER & MEMORY MAP . 17 4 FLASH PROGRAM MEMORY 21 4.1 INTRODUCTION 21 4.2 MAIN FEATURES . 21 4.3 STRUCTURE . 21 4.3.1 Read-out Protection 21 4.4 ICC INTERFACE 22 4.5 ICP (IN-CIRCUIT PROGRAMMING) . 23 4.6 IAP (IN-APPLICATION PROGRAMMING) . 23 4.7 RELATED DOCUMENTATION . 23 4.7.1 Register Description . 23 5 CENTRAL PROCESSING UNIT . 24 5.1 INTRODUCTION 24 5.2 MAIN FEATURES . 24 5.3 CPU REGISTERS . 24 6 SUPPLY, RESET AND CLOCK MANAGEMENT 27 6.1 PHASE LOCKED LOOP 27 6.2 MULTI-OSCILLATOR (MO) 28 6.3 RESET SEQUENCE MANAGER (RSM) 29 6.3.1 Introduction 29 6.3.2 Asynchronous External RESET pin 29 6.3.3 External Power-On RESET 30 6.3.4 Internal Low Voltage Detector (LVD) RESET 30 6.3.5 Internal Watchdog RESET 30 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) 31 6.4.1 Low Voltage Detector (LVD) . 31 6.4.2 Auxiliary Voltage Detector (AVD) . 32 6.4.3 Clock Security System (CSS) 34 6.4.4 Low Power Modes 34 6.4.5 Register Description . 35 7 INTERRUPTS . 36 7.1 INTRODUCTION 36 7.2 MASKING AND PROCESSING FLOW . 36 7.3 INTERRUPTS AND LOW POWER MODES . 38 7.4 CONCURRENT & NESTED MANAGEMENT 38 7.5 INTERRUPT REGISTER DESCRIPTION . 39 7.6 EXTERNAL INTERRUPTS 41 7.6.1 I/O Port Interrupt Sensitivity 41 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . 43 8 POWER SAVING MODES . 45 197 8.1 INTRODUCTION 45 8.2 SLOW MODE . 45 2/197 1