STGAP2HD Datasheet Galvanically isolated 4 A dual gate driver Features High voltage rail up to 1200 V Driver current capability: 4 A sink/source 25 C dV/dt transient immunity 100 V/ns Overall input-output propagation delay: 75 ns Separate sink and source option for easy gate driving configuration 4 A Miller CLAMP UVLO function Configurable interlocking function Dedicated SD and BRAKE pins Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shutdown protection Standby function 6 kV galvanic isolation Wide Body SO-36W Application Motor driver for industrial drives, factory automation, home appliances and fans 600/1200 V inverters Battery chargers Product status link Induction heating STGAP2HD Welding UPS Product label Power supply units DC-DC converters Power Factor Correction Description The STGAP2HD is a dual gate driver which provides galvanic isolation between each gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A current capability and rail-to-rail outputs, making it suitable for mid and high power applications such as power conversion and industrial motor driver inverters. The separated output pins allow to independently optimize turn-on and turn-off by using dedicated gate resistors, while the Miller CLAMP function allows avoiding gate spikes during fast commutations in half-bridge topologies. The device integrates protection functions: dedicated SD and BRAKE pins are available, UVLO and thermal shutdown are included to easily design high reliability systems. In half-bridge topologies the interlocking function prevents outputs from being high at the same time, avoiding shoot-through conditions in case of wrong logic input commands. The interlocking function can be disabled by a dedicated configuration pin, so to allow independent and parallel operation of the two channels. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption. DS13652 - Rev 1 - October 2021 www.st.com For further information contact your local STMicroelectronics sales office.STGAP2HD Block diagram 1 Block diagram Figure 1. Block diagram VH A VDD UVLO VH GON A Level Floating INA Section Shifter Control GOFF A Logic CLAMP A INB I GNDISO A S Floating ground A + Control O SD VCLAMPth L Logic A VH B T I O BRAKE N UVLO VH GON B Floating Level Shifter Section Control VDD GOFF B Logic CLAMP B iLOCK GND GNDISO B Floating ground B + VCLAMPth DS13652 - Rev 1 page 2/23