STGAP2SICS STMicroelectronics

STGAP2SICS Datasheet Galvanically isolated 4 A single gate driver for SiC MOSFETs Features High voltage rail up to 1200 V Driver current capability: 4 A sink/source 25C dV/dt transient immunity 100 V/ns in full temperature range Overall input-output propagation delay: 75 ns Separate sink and source option for easy gate driving configuration 4 A Miller CLAMP dedicated pin option UVLO function Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shut-down protection Standby function 6 kV galvanic isolation Wide body SO-8W package Description The STGAP2SICS is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in Product status link two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. STGAP2SICS The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations Product label provide high flexibility and bill of material reduction for external components. The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shut down are included to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay is less than 75 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption. DS13402 - Rev 3 - October 2021 www.st.com For further information contact your local STMicroelectronics sales office. STGAP2SICS Block diagram 1 Block diagram Figure 1. Block diagram - Single output and Miller Clamp configuration VH VDD I UVLO S IN+ VH O Level Floating GOUT Section Shifter L Control Control A Logic Logic T CLAMP IN- I O GNDISO N Floating ground A + GND VCLAMPth Figure 2. Block diagram - Separate output configuration VH VDD I UVLO S IN+ VH O Floating Level GON Shifter Section L Control Control A Logic Logic T GOFF IN- I O GNDISO N Floating ground GND DS13402 - Rev 3 page 2/23