STGAP2SICSNTR STMicroelectronics

STGAP2SICSN Datasheet Galvanically isolated 4 A single gate driver for SiC MOSFETs Features High voltage rail up to 1700 V Driver current capability: 4 A sink/source 25 C dV/dt transient immunity 100 V/ns in full temperature range Overall input-output propagation delay: 75 ns Separate sink and source option for easy gate driving configuration 4 A Miller CLAMP dedicated pin option UVLO function Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shutdown protection Standby function 4.8 kV isolation PK Narrow body SO-8 Application Motor driver for home appliances, factory automation, industrial drives and fans. 600/1200 V inverters Battery chargers Induction heating Welding Product status link UPS STGAP2SICSN Power supply units Product label DC-DC converters Power Factor Correction Description The STGAP2SICSN is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components. The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shutdown are included to easily design high reliability systems. Dual input pins allow choosing the control signal polarity and also implementing HW interlocking protection in order to avoid cross-conduction in case of controller malfunction. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption. DS13757 - Rev 2 - October 2021 www.st.com For further information contact your local STMicroelectronics sales office. STGAP2SICSN Block diagram 1 Block diagram Figure 1. Block diagram - Single output and Miller Clamp configuration VH VDD I UVLO S IN+ VH O Floating Level GOUT Shifter Section L Control Control A Logic Logic T CLAMP IN- I O GNDISO N Floating ground A + GND VCLAMPth Figure 2. Block diagram - Separate outputs configuration VH VDD I UVLO S IN+ VH O Level Floating GON Section Shifter L Control Control A Logic Logic T GOFF IN- I O GNDISO N Floating ground GND DS13757 - Rev 2 page 2/23