STM32F205xx STM32F207xx Arm -based 32-bit MCU, 150 DMIPs, up to 1 MB Flash/128+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces and camera Datasheet - production data Features Core: Arm 32-bit Cortex -M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution LQFP64 (10 10 mm) WLCSP64+2 UFBGA176 performance from Flash memory, MPU, (0.400 mm pitch) (10 10 mm) LQFP100 (14 14 mm) 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1) LQFP144 (20 20mm) Memories LQFP176 (24 24 mm) Up to 1 Mbyte of Flash memory 512 bytes of OTP memory Up to 140 I/O ports with interrupt capability: Up to 128 + 4 Kbytes of SRAM Up to 136 fast I/Os up to 60 MHz Flexible static memory controller that Up to 138 5 V-tolerant I/Os supports Compact Flash, SRAM, PSRAM, Up to 15 communication interfaces NOR and NAND memories 2 Up to three I C interfaces (SMBus/PMBus) LCD parallel interface, 8080/6800 modes Up to four USARTs and two UARTs Clock, reset and supply management (7.5 Mbit/s, ISO 7816 interface, LIN, IrDA, From 1.8 to 3.6 V application supply + I/Os modem control) POR, PDR, PVD and BOR Up to three SPIs (30 Mbit/s), two with 4 to 26 MHz crystal oscillator 2 muxed I S to achieve audio class accuracy Internal 16 MHz factory-trimmed RC via audio PLL or external PLL 32 kHz oscillator for RTC with calibration 2 CAN interfaces (2.0B Active) Internal 32 kHz RC with calibration SDIO interface Low-power modes Advanced connectivity Sleep, Stop and Standby modes USB 2.0 full-speed device/host/OTG V supply for RTC, 20 32 bit backup controller with on-chip PHY BAT registers, and optional 4 Kbytes backup USB 2.0 high-speed/full-speed SRAM device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI 3 12-bit, 0.5 s ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII 2 12-bit D/A converters 8- to 14-bit parallel camera interface General-purpose DMA: 16-stream controller (48 Mbyte/s max.) with centralized FIFOs and burst support CRC calculation unit Up to 17 timers 96-bit unique ID Up to twelve 16-bit and two 32-bit timers, up to 120 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input Debug mode: Serial wire debug (SWD), JTAG, and Cortex -M3 Embedded Trace Macrocell July 2020 DS6329 Rev 18 1/181 This is information on a product in full production. www.st.comSTM32F20xxx Table 1. Device summary Reference Part numbers STM32F205RB, STM32F205RC, STM32F205RE, STM32F205RF, STM32F205RG STM32F205xx STM32F205VB, STM32F205VC, STM32F205VE, STM32F205VF, STM32F205VG STM32F205ZC, STM32F205ZE, STM32F205ZF, STM32F205ZG STM32F207IC, STM32F207IE, STM32F207IF, STM32F207IG STM32F207xx STM32F207VC, STM32F207VE, STM32F207VF, STM32F207VG STM32F207ZC, STM32F207ZE, STM32F207ZF, STM32F207ZG 2/181 DS6329 Rev 18