STM8AF6246 STM8AF6248 STM8AF6266 STM8AF6268 Automotive 8-bit MCU, with up to 32 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V Datasheet - production data Features Core Max f : 16 MHz CPU Advanced STM8A core with Harvard architecture and 3-stage pipeline LQFP48 LQFP32 VFQFPN32 (7x7 mm) (7x7 mm) (5x5 mm) Average 1.6 cycles/instruction resulting in Window and independent watchdog timers 10 MIPS at 16 MHz f for industry CPU standard benchmark Communication interfaces Memories LINUART Flash Program memory: 16 to 32 Kbyte LIN 2.2 compliant, master/slave modes Flash data retention 20 years at 55 C with automatic resynchronization after 1 kcycle SPI interface up to 8 Mbit/s or f /2 MASTER 2 Data memory: 0.5 to 1 Kbyte true data I C interface up to 400 Kbit/s EEPROM endurance 300 kcycle Analog-to-digital converter (ADC) RAM: 2 Kbyte 10-bit accuracy, 2LSB TUE accuracy, 2LSB Clock management TUE linearity ADC and up to 10 multiplexed Low-power crystal resonator oscillator with channels with individual data buffer external clock input Analog watchdog, scan and continuous Internal, user-trimmable 16 MHz RC and sampling mode low-power 128 kHz RC oscillators I/Os Clock security system with clock monitor Up to 38 user pins including 10 HS I/Os Reset and supply management Highly robust I/O design, immune against Wait/auto-wakeup/Halt low-power modes current injection with user definable clock gating Operating temperature up to 150 C Low consumption power-on and power- Qualification conforms to AEC-Q100 rev G down reset Interrupt management Nested interrupt controller with 32 vectors Up to 34 external interrupts on 5 vectors Timers Up to 2 general purpose 16-bit PWM timers with up to 3 CAPCOM channels each (IC, OC or PWM) Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead- time insertion and flexible synchronization 8-bit AR basic timer with 8-bit prescaler Auto-wakeup timer June 2015 DocID14952 Rev 10 1/99 This is information on a product in full production. www.st.comContents STM8AF6246/48/66/68 Contents 1 Introduction 9 2 Description 10 3 Product line-up 11 4 Block diagram . 12 5 Product overview 14 5.1 STM8A central processing unit (CPU) . 14 5.1.1 Architecture and registers . 14 5.1.2 Addressing . 14 5.1.3 Instruction set 14 5.2 Single wire interface module (SWIM) and debug module (DM) 15 5.2.1 SWIM . 15 5.2.2 Debug module 15 5.3 Interrupt controller 15 5.4 Flash program and data EEPROM 15 5.4.1 Architecture 15 5.4.2 Write protection (WP) 16 5.4.3 Protection of user boot code (UBC) 16 5.4.4 Read-out protection (ROP) 17 5.5 Clock controller . 17 5.5.1 Features . 17 5.5.2 16 MHz high-speed internal RC oscillator (HSI) 18 5.5.3 128 kHz low-speed internal RC oscillator (LSI) . 19 5.5.4 16 MHz high-speed external crystal oscillator (HSE) . 19 5.5.5 External clock input 19 5.5.6 Clock security system (CSS) . 19 5.6 Low-power operating modes 20 5.7 Timers . 20 5.7.1 Watchdog timers 20 5.7.2 Auto-wakeup counter . 21 5.7.3 Beeper 21 2/99 DocID14952 Rev 10