VNQ6040S-E STMicroelectronics

VNQ6040S-E Quad channel high-side driver Datasheet - production data Description The VNQ6040S-E is a device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads PowerSSO-36 directly connected to ground. The device is protected against voltage transient on V pin. CC Features Programming, control and diagnostics are implemented via the SPI bus. General 16 bit ST-SPI for full and diagnostic An analog current feedback for each channel is Programmable BULB/LED mode connected to the CURRENT-SENSE pin via a multiplexer. A CS SYNC pin delivers a Integrated PWM and phase shift generation synchronous signal for sampling the current unit sense while the corresponding output is on. 160 Hz internal PWM fallback frequency Advanced limp home functionalities for The device detects open-load for both on-state robust fail-safe system and off-state conditions. Very low standby current Real time diagnostic is available through the SPI Optimized electromagnetic emissions bus (open-load, output short to V , CC Very low electromagnetic susceptibility overtemperature, communication error). In compliance with the 2002/95/EC Output current limitation protects the device in an Diagnostic overload condition. The device can limit the dissipated power to a safe level up to thermal Multiplex proportional load current sense shutdown intervention. Thermal shutdown can be Synchronous diagnostic of overload and configured as latched off or with automatic restart. short to GND, output shorted to V , CC ON-state and OFF-state open-load The device enters a limp home mode in case of Programmable case overtemperature loss of digital supply (V ), reset of digital DD warning memory or CSN monitoring time-out event. In this Protections mode states of channel 0, 1, 2 or 3 are respectively controlled by four dedicated pins IN0, Load current limitation IN1, IN2 and IN3. Each channel can be Self limiting of fast thermal transients programmed in BULB/LED mode. Power limitation and overtemperature shutdown (latching off or autorestart) Undervoltage shutdown Overvoltage clamp Reverse battery protected through power outputs self turn-on (no external components) Load dump protected Protection against loss of ground March 2015 DocID18061 Rev 11 1/73 This is information on a product in full production. www.st.comContents VNQ6040S-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.2 Fail Safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.3 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.4 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.5 Sleep mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.6 Sleep mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.7 Battery undervoltage mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Programmable functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.1 Outputs configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.2 Case over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.3 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.4 Open-load ON-state detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.5 Open-load OFF-state detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.6 Current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3 Test mode (reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 SPI communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.1 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.2 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.3 SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 SDI, SDO format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.2 Global status byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.3 Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.1 Address 00h - Control Register (CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.2 Address 01h - SPI Output Control Register (SOCR) . . . . . . . . . . . . . . . 34 3.3.3 Address 02h - Direct Input Enable Control Register (DIENCR) . . . . . . . 35 2/73 DocID18061 Rev 11