SEN01G64D1BH1MT-25WR Swissbit

Data Sheet Rev.1.3 23.11.2010 1GB DDR2 SDRAM SO-DIMM Features: 200 Pin SO-DIMM 200-pin 64-bit Small Outline, Dual-In-Line Double Data Rate Synchronous DRAM Module SEN01G64D1BH1MT-25R Module organization: single rank 128M x 64 1GB PC2-6400 in FBGA Technology VDD = 1.8V 0.1V, V 1.8V 0.1V DDQ RoHS compliant 1.8V I/O ( SSTL 18 compatible) Auto Refresh (CBR) and Self Refresh 8k Refresh every 64ms Options: Serial Presence Detect with EEPROM Gold-contact pad Data Rate / Latency Marking This module is fully pin and functional compatible to DDR2 800 MT/s CL6 -25 the JEDEC PC2-6400 spec. and JEDEC- Standard DDR2 667 MT/s CL5 -30 MO-224. (see www.jedec.org) DDR2 533 MT/s CL4 -37 The pcb and all components are manufactured according to the RoHS compliance specification Module Density EU Directive 2002/95/EC Restriction of Hazardous 1GB with 8 dies and 1 rank Substances (RoHS) Standard Grade (T ) 0C to 70C A DDR2 - SDRAM component MICRON (T ) 0C to 85C C MT47H128M8CF-25 DIE-Revision H Grade E (T ) 0C to 85C A 128Mx8 DDR2 SDRAM in FBGA-60 package (T ) 0C to 95C C Four bit prefetch architecture Grade W (T ) -40C to 85C A (T ) -40C to 95C DLL to align DQ and DQS transitions with CK C Eight internal device banks for concurrent operation * The refresh rate has to be doubled when 85C>T >95C C Programmable CAS latency (CL) Posted CAS additive latency (AL) Environmental Requirements: WRITE latency = READ latency 1 t CK Programmable burst length: 4 or 8 Operating temperature (ambient) standard Grade 0C to 70C Adjustable data-output drive strength Grade E 0C to 85C On-die termination (ODT) Grade W -40C to 85C Operating Humidity 10% to 90% relative humidity, noncondensing 1 Figure: mechanical dimensions Operating Pressure 105 to 69 kPa (up to 10000 ft.) Storage Temperature -55C to 100C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50C 1 if no tolerances specified 0.15mm Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 1 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info swissbit.com of 14 Data Sheet Rev.1.3 23.11.2010 This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Dual-In-line Memory Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high- speed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK ). READ and WRITE accesses to a DDR2 SDRAM module is burst-oriented accesses start at a selected location and continue for a Figure 1: Mechanical Dimensions programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving power-down mode. All inputs and all full drive-strength outputs are SSTL 18 compatible. The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial 2 EEPROM using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the SO-DIMM manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR2 SDRAMs used Row Device Bank Column Refresh Module Addr. Select Addr. Bank Select 128M x 64bit 8 x 128M x 8bit (1024Mbit) 14 BA0, BA1,BA2 10 8k S0 Module Dimensions in mm 67.60 (long) x 30 (high) x 3.80 max (thickness) Timing Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SEN01G64D1BH1MT-25 E/W R 1024 MB 6.4 GB/s 2.5ns/800MT/s 6-6-6 SEN01G64D1BH1MT-30 E/W R 1024 MB 5.3 GB/s 3.0ns/667MT/s 5-5-5 SEN01G64D1BH1MT-37 E/W R 1024 MB 4.26 GB/s 3.75ns/533MT/s 4-4-4 Pin Name A0-9, A11 A13 Address Inputs A10/AP Address Input / Autoprecharge Bit BA0 BA2 Bank Address Inputs DQ0 DQ63 Data Input / Output DM0-DM7 Input Data Mask DQS0 - DQS7 Data Strobe, positive line DQS0 - DQS7 Data Strobe, negative line (only used when differential data strobe mode is enabled) RAS Row Address Strobe CAS Column Address Strobe WE Write Enable CKE0 Clock Enable CK0 CK1 Clock Inputs, positive line Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 2 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info swissbit.com of 14