TSM900N10 Taiwan Semiconductor N-Channel Power MOSFET 100V, 15A, 90m FEATURES KEY PERFORMANCE PARAMETERS 100% avalanche tested PARAMETER VALUE UNIT Low gate charge for fast switching V 100 V DS Pb-free plating V = 10V GS 90 RoHS compliant R (max) m DS(on) Halogen-free mold compound V = 4.5V 100 GS Q 9.3 nC g APPLICATION Networking Load Switching LED Lighting Control AC-DC Secondary Rectification TO-251S TO-252 (IPAK SL) (DPAK) Notes: Moisture sensitivity level: level 3. Per J-STD-020 ABSOLUTE MAXIMUM RATINGS (T = 25C unless otherwise noted) A PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V 100 V DS Gate-Source Voltage V 20 V GS T = 25C 15 C (Note 1) Continuous Drain Current I A D T = 100C 9.5 C (Note 2) Pulsed Drain Current I 60 A DM Total Power Dissipation T = 25C P 50 W C DTOT (Note 3) Single Pulsed Avalanche Energy E 18 mJ AS (Note 3) Single Pulsed Avalanche Current I 6 A AS Operating Junction and Storage Temperature Range T , T - 55 to +150 C J STG THERMAL PERFORMANCE PARAMETER SYMBOL LIMIT UNIT Junction to Case Thermal Resistance R 2.5 C/W JC Junction to Ambient Thermal Resistance R 62 C/W JA Notes: R is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined JA at the solder mounting surface of the drain pins. R is guaranteed by design while R is determined by the users board JA CA design. R shown below for single device operation on FR-4 PCB in still air. JA Document Number: DS P0000173 1 Version: A15 TSM900N10 Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (T = 25C unless otherwise noted) A PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 4) Static Drain-Source Breakdown Voltage V = 0V, I = 250A BV 100 -- -- V GS D DSS Gate Threshold Voltage V = V , I = 250A V 1.2 1.6 2.5 DS GS D GS(TH) V Gate Body Leakage V = 20V, V = 0V I -- -- 100 nA GS DS GSS Zero Gate Voltage Drain Current V = 100V, V = 0V I -- -- 1 DS GS DSS A V = 10V, I = 5A -- 72 90 GS D Drain-Source On-State Resistance R m DS(on) V = 4.5V, I = 3A 75 100 GS D (Note 5) Dynamic Total Gate Charge Q -- 9.3 -- g V = 48V, I = 5A, DS D Gate-Source Charge Q -- 2.1 -- gs nC V = 10V GS Gate-Drain Charge Q -- 1.8 -- gd Input Capacitance C -- 1480 -- iss V = 50V, V = 0V, DS GS Output Capacitance C -- 480 -- pF oss f = 1.0MHz Reverse Transfer Capacitance C -- 35 -- rss Gate Resistance F = 1MHz, open drain R -- 1.3 -- g (Note 6) Switching Turn-On Delay Time t -- 2.9 -- d(on) V = 30V, DD Turn-On Rise Time t -- 9.5 -- r R = 3.3, ns GEN Turn-Off Delay Time t -- 18.4 -- d(off) I = 1A, V = 10V, D GS Turn-Off Fall Time t -- 5.3 -- f (Note 4) Source-Drain Diode Forward On Voltage I = 3.3A, V = 0V V -- -- 1 V S GS SD Continuous Drain-Source Diode 15 I -- -- A S V =V =0V, Force Current G D Pulse Drain-Source Diode I -- -- 60 A SM Notes: 1. Current limited by package 2. Pulse width limited by the maximum junction temperature o 3. L = 0.1mH, I = 6A, V = 50V, R = 25, Starting T = 25 C AS DD G J 4. Pulse test: PW 300s, duty cycle 2% 5. For DESIGN AID ONLY, not subject to production testing. 6. Switching time is essentially independent of operating temperature. Document Number: DS P0000173 2 Version: A15