74VHCV573FT(BJ) Toshiba

74VHCV573FT CMOS Digital Integrated Circuits Silicon Monolithic 74VHCV573FT74VHCV573FT74VHCV573FT74VHCV573FT 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description Octal Schmitt D-Type Latch with 3-State Outputs 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74VHCV573FT is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). When the OE input is high, the eight outputs are in a high impedance state. Input pin have hysteresis between the positive-going and negative-going thresholds. Thus the 74VHCV573FT is capable of squaring up transitions of slowly changing input signals and provides an improved noise immunity. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, etc. Note: Output in off-state. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: T = -40 to 125 opr (3) High speed: t = 5.0 ns (typ.) at V = 5.0 V pd CC (4) Low power dissipation: I = 2.0 A (max) at T = 25 CC a (5) Wide operating voltage range: V = 1.8 V to 5.5 V CC(opr) (6) Output current: I /I = 16 mA (min)(V = 4.5 V) OH OL CC (7) Power-down protection is provided on all inputs and outputs. (8) Pin and function compatible with the 74 series (74AC/HC/AHC/LV etc.) 573 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 4. 4. 4. 4. PackagingPackagingPackagingPackaging TSSOP20B Start of commercial production 2014-07 2016 Toshiba Corporation 2016-08-05 1 Rev.3.074VHCV573FT 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 7. 7. 7. 7. Truth TableTruth TableTruth TableTruth Table Input Input Input Output OE LE D H X X Z L L X Qn L H L L L H H H X: Don t care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to low logic level. 2016 Toshiba Corporation 2016-08-05 2 Rev.3.0