TC58BYG0S3HBAI4 Toshiba

TC58BYG0S3HBAI4 MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 1 GBIT (128M 8 BIT) CMOS NAND E PROM DESCRIPTION The TC58BYG0S3HBAI4 is a single 1.8V 1Gbit (1,107,296,256 bits) NAND Electrically Erasable and 2 Programmable Read-Only Memory (NAND E PROM) organized as (2048 + 64) bytes 64 pages 1024 blocks. The device has a 2112- byte static register which allows program and read data to be transferred between the register and the memory cell array in 2112-bytes increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes 64 pages). The TC58BYG0S3HBAI4 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. The TC58BYG0S3HBAI4 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected internally. FEATURES Organization x8 Memory cell array 2112 64K 8 Register 2112 8 Page size 2112 bytes Block size (128K + 4K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, ECC Status Read Mode control Serial input/output Command control Number of valid blocks Min 1004 blocks Max 1024 blocks Power supply VCC = 1.7V to 1.95V Access time Cell array to register 40 s typ. Read Cycle Time 25 ns min (C =30pF) L Program/Erase time Auto Page Program 330 s/page typ. Auto Block Erase 3.5 ms/block typ. Operating current Read (25 ns cycle) 30 mA max Program (avg.) 30 mA max Erase (avg.) 30 mA max Standby 50 A max Package P-TFBGA63-0911-0.80CZ (Weight: 0.15 g typ.) 8bit ECC for each 528Bytes is implemented on a chip. 2012-2018 Toshiba Memory Corporation 2018-06-01C 1 TC58BYG0S3HBAI4 PIN ASSIGNMENT (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 A NC NC NC NC B NC NC NC C ALE V CE WE WP SS RY/BY D NC RE CLE NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC NC NC NC H NC I/O1 NC NC NC V CC J NC I/O2 NC V I/O6 I/O8 CC K V I/O3 I/O4 I/O5 I/O7 V SS SS L NC NC NC NC M NC NC NC NC PIN NAMES I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect RY/BY Ready/Busy V Power supply CC V Ground SS NC No Connection 2012-2018 Toshiba Memory Corporation 2018-06-01C 2