TC74AC161,163P/F/FN/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC161P,TC74AC161F,TC74AC161FN,TC74AC161FT TC74AC163P,TC74AC163F,TC74AC163FN,TC74AC163FT Synchronous Presettable 4-Bit Binary Counter TC74AC161P/F/FN/FT Asynchronous Clear Note: xxxFN (JEDEC SOP) is not available in Japan. TC74AC163P/F/FN/FT Synchronous Clear TC74AC161P, TC74AC163P The TC74AC161 and 163 are advanced high speed CMOS SYNCHRONOUS PRESETTABLE COUNTERs fabricated with 2 silicon gate and double-layer metal wiring C MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The CK input is active on the rising edge. Both LOAD and CLR inputs are active on low logic level. TC74AC161F, TC74AC163F Presetting of these ICs is synchronous to the rising edge of CK. The clear function of the TC74AC163 is synchronous to CK, while the TC74AC161 are cleared asynchronously. Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC161FN, TC74AC163FN Features High speed: f = 170 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 8 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Symmetrical output impedance: I = I = 24 mA (min) OH OL Capability of driving 50 transmission lines. Balanced propagation delays: t t TC74AC161FT, TC74AC163FT pLH pHL Wide operating voltage range: V = 2 to 5.5 V CC (opr) Pin and function compatible with 74F161/163 Weight DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) TSSOP16-P-0044-0.65A : 0.06 g (typ.) 1 2007-10-01 TC74AC161,163P/F/FN/FT Pin Assignment 1 16 V CLR CC CK 2 15 Carry Output A 14 QA 3 B 4 13 QB C 5 12 QC D 6 11 QD ENP 7 10 ENT GND 8 9 LOAD (top view) IEC Logic Symbol TC74AC161 TC74AC163 CTRDIV 16 CTRDIV 16 (1) (1) CLR CT = 0 5CT = 0 CLR (9) (9) LOAD M1 LOAD M1 M2 M2 (15) (15) 3CT = 15 Carry Output 3CT = 15 Carry Output (10) (10) G3 G3 ENT ENT (7) (7) G4 G4 ENP ENP (2) (2) CK C5/2, 3, 4+ CK C5/2, 3, 4+ (3) (14) (3) (14) A 1, 5D (1) QA A 1, 5D (1) QA (4) (13) (4) (13) B (2) QB B (2) QB (5) (12) (5) (12) C (4) QC C (4) QC (6) (11) (6) (11) D (8) QD D (8) QD Truth Table (Note) Inputs Outputs Function CLR CLR CK CK LOAD ENP ENT QA QB QC QD (161) (163) (161) (163) L L X X X X L L L L Reset to 0 H H L X X Preset Data A B C D H H H X L No Change No Count H H H L X No Change No Count H H H H H Count Up Count H X X X X No Change No Count Note: X: Dont care A, B, C, D: Logic level of data inputs Carry: Carry = ENTQAQBQCQD 2 2007-10-01