TC74HC237AF(F) Toshiba

TC74HC237AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC237AP, TC74HC237AF 3-to-8 Line Decoder/Latch The TC74HC237A is a high speed CMOS 3-to-8 LINE TC74HC237AP DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It is composed of a 3-bit input latches with a common GL enable input and 3-to-8 line decoder with enable inputs G1 and G2 . The 3-bit binary data is stored into the input latch on the high level of GL . The value of this data determines which one of the outputs will go low. When the enable input G1 is held low or G2 is held high, TC74HC237AF decoding function is inhibited and all the 8 outputs go high. The two enable inputs are provided to ease cascade connection and permits the application address decoder for memory system. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: t = 12 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 4 A (max) at Ta = 25C CC Weight DIP16-P-300-2.54A : 1.00 g (typ.) High noise immunity: V = V = 28% V (min) NIH NIL CC SOP16-P-300-1.27A : 0.18 g (typ.) Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC Pin and function compatible with 74LS237 Pin Assignment Start of commercial production 1988-05 1 2014-03-01 TC74HC237AP/AF IEC Logic Symbol Truth Table Inputs Outputs Enable Address Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 GL G2 G1 C B A X X L X X X L L L L L L L L X H X X X X L L L L L L L L L L H L L L H L L L L L L L L L H L L H L H L L L L L L L L H L H L L L H L L L L L L L H L H H L L L H L L L L L L H H L L L L L L H L L L L L H H L H L L L L L H L L L L H H H L L L L L L L H L L L H H H H L L L L L L L H Depends upon the address previously applied while GL was H L H X X X at a low level X: Dont care System Diagram 2 2014-03-01