TC74HC245AF(EL,F) Toshiba

TC74HC245AP/AF,640AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC245AP, TC74HC245AF TC74HC640AP, TC74HC640AF Octal Bus Transceiver TC74HC245AP/AF 3-State, Non-Inverting TC74HC245AP, TC74HC640AP TC74HC640AP/AF 3-State, Inverting The TC74HC245A, 640A are high speed CMOS OCTAL BUS 2 TRANSCEIVERs fabricated with silicon gate C MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. They are intended for two-way asynchronous communication between data busses. The direction of data transmission is TC74HC245AF, TC74HC640AF determined by the level of the DIR input. The enable input ( G ) can be used to disable the device so that the busses are effectively isolated. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features (Note 1)(Note 2) High speed: t = 10 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 4 A (max) at Ta = 25C Weight CC DIP20-P-300-2.54A : 1.30 g (typ.) High noise immunity: V = V = 28% V (min) NIH NIL CC SOP20-P-300-1.27A : 0.22 g (typ.) Output drive capability: 15 LSTTL loads Symmetrical output impedance: I = I = 6 mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC Pin and function compatible with 74LS245/640 Note 1: Do not apply a signal to any bus terminal when it is in the output mode. Damage may result. Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull down resistors. Start of commercial production 1986-05 1 2014-03-01 TC74HC245AP/AF,640AP/AF Pin Assignment TC74HC245A TC74HC640A IEC Logic Symbol TC74HC245A TC74HC640A Truth Table Inputs Function Outputs G DIR A Bus B Bus HC245A HC640A L L Output Input A = B A = B L H Input Output B = A B = A H X Z Z Z X: H or L Z: High impedance 2 2014-03-01