TC74LCX138FT(SPL) Toshiba

TC74LCX138F/FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LCX138F, TC74LCX138FT, TC74LCX138FK Low-Voltage 3-to-8 Line Decoder with 5-V Tolerant Inputs and Outputs The TC74LCX138 is a high-performance CMOS 3-to-8 decoder. TC74LCX138F Designed for use in 3.3-V systems, it achieves high-speed operation while maintaining the CMOS low-power dissipation. The device is designed for low-voltage (3.3 V) V applications, CC but it could be used to interface to 5-V supply environment for inputs. When the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade TC74LCX138FT connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge. Features Low-voltage operation: V = 1.65 to 3.6 V CC High-speed operation: t = 6.0 ns (max) (V = 3.0 to 3.6 V) pd CC TC74LCX138FK Ouput current: I /I = 24 mA (min) (V = 3.0 V) OH OL CC Latch-up performance: 500 mA Available in JEITA SOP, TSSOP and VSSOP (US) Power-down protection provided on all inputs and outputs Pin and function compatible with the 74 series (74AC/VHC/HC/F/ALS/LS etc.) 138 type W Weight SOP16-P-300-1.27A : 0.18 g (typ.) TSSOP16-P-0044-0.65A : 0.06 g (typ.) VSSOP16-P-0030-0.50 : 0.02 g (typ.) Note: The Electrical Characteristics of V =1.80.15V is only applicable for products which manufactured CC from January 2009 onward. Start of commercial production 1994-10 1 2014-03-01 TC74LCX138F/FT/FK Pin Assignment (top view) A 1 16 V CC B 2 15 Y0 C 3 14 Y1 G2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 IEC Logic Symbol Bin/Oct (15) (1) Dmux (15) 0 0 Y0 A 0 Y0 (1) (14) (2) 0 (14) 1 1 A 1 Y1 B G Y 1 (2) (13) (3) 7 (13) 2 2 B 2 Y2 C 2 Y 2 (3) (12) (12) 3 3 C 4 Y3 Y3 (11) (6) & (11) 4 4 Y4 G1 Y 4 (6) & (10) (4) (10) 5 5 G1 Y5 G2A Y5 (4) (9) (5) (9) 6 6 G2A EN Y6 G2B Y6 (5) (7) (7) 7 7 G2B Y7 Y 7 Truth Table Inputs Outputs Enable Select Selected Output Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y 7 G1 G2A G2B C B A L X X X X X H H H H H H H H None X H X X X X H H H H H H H H None X X H X X X H H H H H H H H None H L L L L L L H H H H H H H Y0 H L L L L H H L H H H H H H Y 1 H L L L H L H H L H H H H H Y 2 H L L L H H H H H L H H H H Y 3 H L L H L L H H H H L H H H Y 4 H L L H L H H H H H H L H H Y 5 H L L H H L H H H H H H L H Y6 H L L H H H H H H H H H H L Y 7 X: Dont care 2 2014-03-01