TC74ACT299P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT299P,TC74ACT299F 8-Bit PIPO Shift Register with Asynchronous Clear TC74ACT299P The TC74ACT299 is an advanced high speed CMOS 8-BIT PIPO SHIFT REGISTER fabricated with silicon gate and 2 double-layer metal wiring C MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TLL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. TC74ACT299F It has a four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA) controlled by the two selection inputs (S0, S1). When one or both enable ( G1 , G2 ) are high, the eight I/O outputs are forced to the high-impedance state however, sequential operation or clearing of the register is not affected. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features (Note 1)(Note 2) Weight High speed: f = 130 MHz (typ.) at V = 5 V max CC DIP20-P-300-2.54A : 1.30 g (typ.) Low power dissipation: I = 8 A (max) at Ta = 25C CC SOP20-P-300-1.27A : 0.22 g (typ.) Compatible with TTL outputs: V = 0.8 V (max) IL V = 2.0 V (min) IH Symmetrical output impedance: I = I = 24 mA (min) OH OL Capability of driving 50 transmission lines. Balanced propagation delays: t t pLH pHL Pin and function compatible with 74F299 Note 1: Do not apply a signal to any bus terminal when it is in the output mode. Damage may result. Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull down resistors. Pin Assignment 1 2007-10-01 TC74ACT299P/F IEC Logic Symbol Truth Table Inputs/ Inputs Outputs Outputs Function Mode Outputs Control Serial Select CLR CK A/QA H/QH QA QH G 1 G 2 S1 S0 SL SR (Note) (Note) Z L H H X X X X X Z Z L L L L X L L X X X L L L L Clear L X L L L X X X L L L L Hold H L L L L X X X QA0 QH0 QA0 QH0 Shift H L H L L X H H QGn H QGn Right H L H L L X L L QGn L QGn Shift H H L L L H X QBn H QBn H Left H H L L L L X QBn L QBn L Load H H H X X X X a h a h Note: When one or both output controls are high, the eight input/output terminals are in the high-impedance state however sequential or clearing of the register is not affected. Z: High impedance Qn0: The level of Qn before the indicated steady-state input conditions were established. Qnn: The level of Qn before the most recent active transition indicated by or . a, h: The level of the steady-state inputs A, H, respectively. X: Dont care 2 2007-10-01