TC74VCX138FT(SPL) Toshiba

TC74VCX138FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VCX138FT, TC74VCX138FK Low Voltage 3-to-8 Line Decoder with 3.6 V Tolerant Inputs and Outputs The TC74VCX138 is a high performance CMOS 3-to-8 decoder TC74VCX138FT which is guaranteed to operate from 1.2-V to 3.6-V. Designed for use in 1.5 V, 1.8 V, 2.5 V or 3.3 V systems, it achieves high speed operation while maintaining the CMOS low power dissipation. It is also designed with over voltage tolerant inputs and outputs up to 3.6 V. When the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs ( Y0 to Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A and G2B inputs are provided to ease cascade TC74VCX138FK connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge. Features Low voltage operation: V = 1.2 to 3.6 V CC High speed operation: t = 3.5 ns (max) (V = 3.0 to 3.6 V) pd CC t = 4.1 ns (max) (V = 2.3 to 2.7 V) pd CC Weight t = 8.2 ns (max) (V = 1.65 to 1.95 V) pd CC TSSOP16-P-0044-0.65A : 0.06 g (typ.) t = 16.4 ns (max) (V = 1.4 to 1.6 V) pd CC VSSOP16-P-0030-0.50 : 0.02 g (typ.) t = 41.0 ns (max) (V = 1.2 V) pd CC 3.6 V tolerant inputs and outputs. Output current: I /I = 24 mA (min) (V = 3.0 V) OH OL CC I /I = 18 mA (min) (V = 2.3 V) OH OL CC I /I = 6 mA (min) (V = 1.65 V) OH OL CC I /I = 2 mA (min) (V = 1.4 V) OH OL CC Latch-up performance: 300 mA ESD performance: Machine model 200 V Human body model 2000 V Package: TSSOP and VSSOP (US) Power down protection is provided on all inputs and outputs. Start of commercial production 2000-09 1 2014-03-01 TC74VCX138FT/FK Pin Assignment (top view) A 1 16 V CC B 2 15 Y0 C 14 Y1 3 G2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 IEC Logic Symbol Bin/Oct Dmux 15 15 0 0 Y0 Y0 1 14 1 14 1 1 A 1 Y1 A 0 Y 1 0 2 13 2 13 2 2 B 2 Y2 B G Y 2 7 3 12 3 12 3 3 C 4 Y3 C 2 Y3 11 11 4 4 Y4 Y 4 & & 6 10 6 10 5 5 G1 Y5 G1 Y5 4 9 4 9 6 6 G2A EN Y6 G2A Y6 5 7 5 7 7 7 G2B Y7 G2B Y 7 Truth Table Inputs Outputs Enable Select Selected Output Y 0 Y1 Y2 Y3 Y4 Y5 Y6 Y 7 G1 G2A G2B C B A L X X X X X H H H H H H H H None X H X X X X H H H H H H H H None X X H X X X H H H H H H H H None H L L L L L L H H H H H H H Y 0 H L L L L H H L H H H H H H Y 1 H L L L H L H H L H H H H H Y 2 H L L L H H H H H L H H H H Y 3 H L L H L L H H H H L H H H Y 4 H L L H L H H H H H H L H H Y 5 H L L H H L H H H H H H L H Y 6 H L L H H H H H H H H H H L Y 7 X: Dont care 2 2014-03-01